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MM74HC73J PDF预览

MM74HC73J

更新时间: 2024-11-16 05:08:31
品牌 Logo 应用领域
美国国家半导体 - NSC 振荡器触发器锁存器
页数 文件大小 规格书
6页 129K
描述
Dual J-K Flip-Flops with Clear

MM74HC73J 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:DIP, DIP14,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.82
Is Samacsys:N其他特性:MASTER SLAVE OPERATION
系列:HC/UHJESD-30 代码:R-GDIP-T14
JESD-609代码:e0长度:19.43 mm
负载电容(CL):50 pF逻辑集成电路类型:J-K FLIP-FLOP
最大频率@ Nom-Sup:21000000 Hz最大I(ol):0.004 A
位数:2功能数量:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 V传播延迟(tpd):160 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:NEGATIVE EDGE宽度:7.62 mm
最小 fmax:25 MHzBase Number Matches:1

MM74HC73J 数据手册

 浏览型号MM74HC73J的Datasheet PDF文件第2页浏览型号MM74HC73J的Datasheet PDF文件第3页浏览型号MM74HC73J的Datasheet PDF文件第4页浏览型号MM74HC73J的Datasheet PDF文件第5页浏览型号MM74HC73J的Datasheet PDF文件第6页 
January 1988  
MM54HC73/MM74HC73  
Dual J-K Flip-Flops with Clear  
General Description  
These J-K Flip-Flops utilize advanced silicon-gate CMOS  
technology. They possess the high noise immunity and low  
power dissipation of standard CMOS integrated circuits.  
These devices can drive 10 LS-TTL loads.  
All inputs are protected from damage due to static dis-  
and ground.  
charge by internal diode clamps to V  
CC  
Features  
Y
These flip-flops are edge sensitive to the clock input and  
change state on the negative going transition of the clock  
pulse. Each one has independent, J, K, CLOCK, and  
CLEAR inputs and Q and Q outputs. CLEAR is independent  
of the clock and accomplished by a low level on the input.  
Typical propagation delay: 16 ns  
Y
Wide operating voltage range: 26V  
Y
Y
Y
Low input current: 1 mA maximum  
Low quiescent current: 40 mA (74HC Series)  
High output drive: 10 LS-TTL loads  
The 54HC/74HC logic family is functionally as well as pin-  
out compatible with the standard 54LS/74LS logic family.  
Connection and Logic Diagrams  
Truth Table  
Dual-In-Line Package  
Inputs  
Outputs  
CLR  
CLK  
J
K
Q
Q
L
X
X
L
X
L
L
Q0  
H
H
Q0  
L
H
H
H
H
H
v
v
v
v
H
H
L
L
H
H
X
L
H
H
X
TOGGLE  
Q0 Q0  
Top View  
TL/F/5072–1  
Order Number MM54HC73 or MM74HC73  
TL/F/5072–2  
TL/F/5072–3  
(1 of 2)  
C
1995 National Semiconductor Corporation  
TL/F/5072  
RRD-B30M115/Printed in U. S. A.  

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