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MM74HC373WM PDF预览

MM74HC373WM

更新时间: 2024-10-29 11:11:23
品牌 Logo 应用领域
安森美 - ONSEMI PC驱动光电二极管逻辑集成电路
页数 文件大小 规格书
9页 293K
描述
3 态八路 D 型锁存

MM74HC373WM 技术参数

是否无铅:不含铅生命周期:Active
包装说明:SOP, SOP20,.4Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:0.47
Samacsys Confidence:Samacsys Status:Released
Samacsys PartID:582308Samacsys Pin Count:20
Samacsys Part Category:Undefined or MiscellaneousSamacsys Package Category:Other
Samacsys Footprint Name:SOIC127P1032X265-20NSamacsys Released Date:2017-01-11 16:35:06
Is Samacsys:N系列:HC/UH
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:12.8015 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.006 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
Prop。Delay @ Nom-Sup:37 ns传播延迟(tpd):280 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

MM74HC373WM 数据手册

 浏览型号MM74HC373WM的Datasheet PDF文件第2页浏览型号MM74HC373WM的Datasheet PDF文件第3页浏览型号MM74HC373WM的Datasheet PDF文件第4页浏览型号MM74HC373WM的Datasheet PDF文件第5页浏览型号MM74HC373WM的Datasheet PDF文件第6页浏览型号MM74HC373WM的Datasheet PDF文件第7页 
DATA SHEET  
www.onsemi.com  
3-STATE Octal D-Type Latch  
MM74HC373  
SOIC20 WB  
CASE 751D05  
General Description  
The MM74HC373 high speed octal Dtype latches utilize advanced  
silicongate CMOS technology. They possess the high noise  
immunity and low power consumption of standard CMOS integrated  
circuits, as well as the ability to drive 15 LSTTL loads. Due  
to the large output drive capability and the 3STATE feature, these  
devices are ideally suited for interfacing with bus lines in a bus  
organized system.  
SOIC20, 300 mils  
CASE 751BJ01  
When the LATCH ENABLE input is HIGH, the Q outputs will  
follow the D inputs. When the LATCH ENABLE goes LOW, data  
at the D inputs will be retained at the outputs until LATCH ENABLE  
returns HIGH again. When a high logic level is applied  
to the OUTPUT CONTROL input, all outputs go to a high impedance  
state, regardless of what signals are present at the other inputs  
and the state of the storage elements.  
TSSOP20 WB  
CASE 948E  
MARKING DIAGRAMS  
SOIC20  
The 74HC logic family is speed, function, and pinout compatible  
with the standard 74LS logic family. All inputs are protected  
20  
HC373A  
AWLYYWW  
from damage due to static discharge by internal diode clamps to V  
and ground.  
CC  
Features  
1
Typical Propagation Delay: 18 ns  
Wide Operating Voltage Range: 2 to 6 V  
Low Input Current: 1 mA Maximum  
Low Quiescent Current: 160 mA Maximum (74 Series)  
Output Drive Capability: 15 LSTTL Loads  
This is a PbFree Device  
TSSOP20  
20  
HC  
373A  
ALYW  
1
LATCH  
ENABLE  
HC373A = Specific Device Code  
V
8Q  
19  
7D  
17  
7Q  
16  
6Q  
15  
6D  
14  
5D  
13  
5Q  
12  
6
A
WL, L  
Y
= Assembly Location  
= Wafer Lot Number  
= Year  
8D  
18  
CC  
20  
11  
WW, YW = Work Week  
Q
D
G
D
G
Q
Q
D
G
D
G
Q
OE  
OE  
OE  
OE  
OE  
OE  
OE  
OE  
ORDERING INFORMATION  
See detailed ordering and shipping information on page 5 of  
this data sheet.  
D
G
Q
2
D
G
Q
Q
6
D
G
D
G
Q
1
3
4
5
7
3D  
8
9
10  
GND  
1Q  
1D  
2D  
2Q  
3Q  
4D  
4Q  
OUTPUT  
CONTROL  
Pin Assignments for SOIC and TSSOP (Top View)  
Figure 1. Connection Diagram  
© Semiconductor Components Industries, LLC, 1983  
1
Publication Order Number:  
November, 2022 Rev. 2  
MM74HC373/D  

MM74HC373WM 替代型号

型号 品牌 替代类型 描述 数据表
MM74HC373WMX ONSEMI

完全替代

3 态八路 D 型锁存
MC74HC373ADWR2G ONSEMI

类似代替

Octal 3−State Non−Inverting Transparent Latch High−Performance Silicon&#
MC74HC373ADWG ONSEMI

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Octal 3−State Non−Inverting Transparent Latch High−Performance Silicon&#

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