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MM74HC374_05 PDF预览

MM74HC374_05

更新时间: 2024-10-28 05:08:31
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
8页 103K
描述
3-STATE Octal D-Type Flip-Flop

MM74HC374_05 数据手册

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September 1983  
Revised May 2005  
MM74HC374  
3-STATE Octal D-Type Flip-Flop  
General Description  
Features  
The MM74HC374 high speed Octal D-Type Flip-Flops uti-  
lize advanced silicon-gate CMOS technology. They pos-  
sess the high noise immunity and low power consumption  
of standard CMOS integrated circuits, as well as the ability  
to drive 15 LS-TTL loads. Due to the large output drive  
capability and the 3-STATE feature, these devices are ide-  
ally suited for interfacing with bus lines in a bus organized  
system.  
Typical propagation delay: 20 ns  
Wide operating voltage range: 2–6V  
Low input current: 1 A maximum  
Low quiescent current: 80 A maximum  
Compatible with bus-oriented systems  
Output drive capability: 15 LS-TTL loads  
These devices are positive edge triggered flip-flops. Data  
at the D inputs, meeting the setup and hold time require-  
ments, are transferred to the Q outputs on positive going  
transitions of the CLOCK (CK) input. When a high logic  
level is applied to the OUTPUT CONTROL (OC) input, all  
outputs go to a high impedance state, regardless of what  
signals are present at the other inputs and the state of the  
storage elements.  
The 74HC logic family is speed, function, and pinout com-  
patible with the standard 74LS logic family. All inputs are  
protected from damage due to static discharge by internal  
diode clamps to VCC and ground.  
Ordering Code:  
Order Number Package Number  
Package Description  
MM74HC374WM  
MM74HC374SJ  
MM74HC374MTC  
MM74HC374N  
M20B  
M20D  
MTC20  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Connection Diagram  
Truth Table  
Pin Assignments for DIP, SOIC, SOP and TSSOP  
Output  
Clock  
Data  
Output  
Control  
L
L
H
L
H
L
L
L
X
X
Q0  
Z
H
X
H
L
X
HIGH Level  
LOW Level  
Don't Care  
Transition from LOW-to-HIGH  
High Impedance State  
Z
Q
The level of the output before steady state input conditions were  
0
established  
Top View  
© 2005 Fairchild Semiconductor Corporation  
DS005336  
www.fairchildsemi.com  

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