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MM74HC390N PDF预览

MM74HC390N

更新时间: 2024-11-28 14:38:15
品牌 Logo 应用领域
德州仪器 - TI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
8页 149K
描述
HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDIP16, DIP-16

MM74HC390N 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.24
其他特性:DIVIDE BY 2 AND DIVIDE BY 5 FUNCTIONS计数方向:UP
系列:HC/UHJESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:21.755 mm
负载电容(CL):50 pF负载/预设输入:NO
逻辑集成电路类型:DECADE COUNTER最大频率@ Nom-Sup:4000000 Hz
最大I(ol):0.004 A工作模式:ASYNCHRONOUS
位数:3功能数量:4
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
传播延迟(tpd):360 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Counters
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:NEGATIVE EDGE
宽度:7.62 mm最小 fmax:24 MHz
Base Number Matches:1

MM74HC390N 数据手册

 浏览型号MM74HC390N的Datasheet PDF文件第2页浏览型号MM74HC390N的Datasheet PDF文件第3页浏览型号MM74HC390N的Datasheet PDF文件第4页浏览型号MM74HC390N的Datasheet PDF文件第5页浏览型号MM74HC390N的Datasheet PDF文件第6页浏览型号MM74HC390N的Datasheet PDF文件第7页 
January 1988  
MM54HC390/MM74HC390  
Dual 4-Bit Decade Counter  
MM54HC393/MM74HC393  
Dual 4-Bit Binary Counter  
General Description  
These counter circuits contain independent ripple carry  
counters and utilize advanced silicon-gate CMOS technolo-  
gy. The MM54HC390/MM74HC390 incorporate dual dec-  
ade counters, each composed of a divide-by-two and a di-  
vide-by-five counter. The divide-by-two and divide-by-five  
counters can be cascaded to form dual decade, dual bi-qui-  
nary, or various combinations up to a single divide-by-100  
counter. The MM54HC393/MM74HC393 contain two 4-bit  
ripple carry binary counters, which can be cascaded to cre-  
ate a single divide-by-256 counter.  
tionally as well as pin equivalent to the 54LS390/74LS390  
and the 54LS393/74LS393, respectively. All inputs are pro-  
tected from damage due to static discharge by diodes to  
V
CC  
and ground.  
Features  
Y
Typical operating frequency: 50 MHz  
Y
Typical propagation delay: 13 ns (Ck to Q )  
A
Y
Y
Y
Wide operating supply voltage range: 26V  
k
Low input current: 1 mA  
Each of the two 4-bit counters is incremented on the high to  
low transition (negative edge) of the clock input, and each  
has an independent clear input. When clear is set high all  
four bits of each counter are set to a low level. This enables  
count truncation and allows the implementation of divide-by-  
N counter configurations.  
Low quiescent supply current: 80 mA maximum  
(74HC Series)  
Y
Fanout of 10 LS-TTL loads  
Each of the counters outputs can drive 10 low power  
Schottky TTL equivalent loads. These counters are func-  
Connection Diagrams  
Dual-In-Line Package  
Dual-In-Line Package  
TL/F/5337–1  
TL/F/5337–2  
Top View  
Top View  
Order Number MM54HC390 or MM74HC390  
Order Number MM54HC393 or MM74HC393  
C
1995 National Semiconductor Corporation  
TL/F/5337  
RRD-B30M105/Printed in U. S. A.  

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