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MM74HC02MTC_NL PDF预览

MM74HC02MTC_NL

更新时间: 2024-10-31 13:11:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
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6页 80K
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MM74HC02MTC_NL 数据手册

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September 1983  
Revised February 1999  
MM74HC02  
Quad 2-Input NOR Gate  
General Description  
Features  
The MM74HC02 NOR gates utilize advanced silicon-gate  
CMOS technology to achieve operating speeds similar to  
LS-TTL gates with the low power consumption of standard  
CMOS integrated circuits. All gates have buffered outputs,  
providing high noise immunity and the ability to drive 10  
LS-TTL loads. The 74HC logic family is functionally as well  
as pin-out compatible with the standard 74LS logic family.  
All inputs are protected from damage due to static dis-  
charge by internal diode clamps to VCC and ground.  
Typical propagation delay: 8 ns  
Wide power supply range: 2–6V  
Low quiescent supply current: 20 µA maximum  
(74HC Series)  
Low input current: 1 µA maximum  
High output current: 4 mA minimum  
Ordering Code:  
Order Number Package Number  
Package Description  
MM74HC02M  
MM74HC02SJ  
MM74HC02MTC  
MM74HC02N  
M14A  
M14D  
MTC14  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. (Tape and Reel not available in N14A.)  
Connection Diagram  
Pin Assignment for DIP, SOIC, SOP and TSSOP  
Top View  
Logic Diagram  
© 1999 Fairchild Semiconductor Corporation  
DS005294.prf  
www.fairchildsemi.com  

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