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MM74HC02SJ PDF预览

MM74HC02SJ

更新时间: 2024-11-23 22:46:07
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 逻辑集成电路光电二极管
页数 文件大小 规格书
6页 80K
描述
Quad 2-Input NOR Gate

MM74HC02SJ 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:SOIC
包装说明:SOP, SOP14,.3针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.15系列:HC/UH
JESD-30 代码:R-PDSO-G14JESD-609代码:e3
长度:10.2 mm负载电容(CL):50 pF
逻辑集成电路类型:NOR GATE最大I(ol):0.004 A
湿度敏感等级:1功能数量:4
输入次数:2端子数量:14
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:RAIL
峰值回流温度(摄氏度):260电源:2/6 V
Prop。Delay @ Nom-Sup:27 ns传播延迟(tpd):113 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:2.1 mm子类别:Gates
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:MATTE TIN端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5.3 mm
Base Number Matches:1

MM74HC02SJ 数据手册

 浏览型号MM74HC02SJ的Datasheet PDF文件第2页浏览型号MM74HC02SJ的Datasheet PDF文件第3页浏览型号MM74HC02SJ的Datasheet PDF文件第4页浏览型号MM74HC02SJ的Datasheet PDF文件第5页浏览型号MM74HC02SJ的Datasheet PDF文件第6页 
September 1983  
Revised February 1999  
MM74HC02  
Quad 2-Input NOR Gate  
General Description  
Features  
The MM74HC02 NOR gates utilize advanced silicon-gate  
CMOS technology to achieve operating speeds similar to  
LS-TTL gates with the low power consumption of standard  
CMOS integrated circuits. All gates have buffered outputs,  
providing high noise immunity and the ability to drive 10  
LS-TTL loads. The 74HC logic family is functionally as well  
as pin-out compatible with the standard 74LS logic family.  
All inputs are protected from damage due to static dis-  
charge by internal diode clamps to VCC and ground.  
Typical propagation delay: 8 ns  
Wide power supply range: 2–6V  
Low quiescent supply current: 20 µA maximum  
(74HC Series)  
Low input current: 1 µA maximum  
High output current: 4 mA minimum  
Ordering Code:  
Order Number Package Number  
Package Description  
MM74HC02M  
MM74HC02SJ  
MM74HC02MTC  
MM74HC02N  
M14A  
M14D  
MTC14  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. (Tape and Reel not available in N14A.)  
Connection Diagram  
Pin Assignment for DIP, SOIC, SOP and TSSOP  
Top View  
Logic Diagram  
© 1999 Fairchild Semiconductor Corporation  
DS005294.prf  
www.fairchildsemi.com  

MM74HC02SJ 替代型号

型号 品牌 替代类型 描述 数据表
74VHC02SJX FAIRCHILD

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