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MM74HC02MTCX_NL PDF预览

MM74HC02MTCX_NL

更新时间: 2024-11-24 04:39:31
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
7页 84K
描述
Quad 2-Input NOR Gate

MM74HC02MTCX_NL 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP14,.25
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.15
系列:HC/UHJESD-30 代码:R-PDSO-G14
JESD-609代码:e3长度:5 mm
负载电容(CL):50 pF逻辑集成电路类型:NOR GATE
最大I(ol):0.004 A湿度敏感等级:1
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:2/6 VProp。Delay @ Nom-Sup:27 ns
传播延迟(tpd):113 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.2 mm
子类别:Gates最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

MM74HC02MTCX_NL 数据手册

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September 1983  
Revised January 2005  
MM74HC02  
Quad 2-Input NOR Gate  
General Description  
Features  
The MM74HC02 NOR gates utilize advanced silicon-gate  
CMOS technology to achieve operating speeds similar to  
LS-TTL gates with the low power consumption of standard  
CMOS integrated circuits. All gates have buffered outputs,  
providing high noise immunity and the ability to drive 10  
LS-TTL loads. The 74HC logic family is functionally as well  
as pin-out compatible with the standard 74LS logic family.  
All inputs are protected from damage due to static dis-  
charge by internal diode clamps to VCC and ground.  
Typical propagation delay: 8 ns  
Wide power supply range: 2–6V  
Low quiescent supply current: 20 µA maximum  
(74HC Series)  
Low input current: 1 µA maximum  
High output current: 4 mA minimum  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
MM74HC02M  
MM74HC02SJ  
MM74HC02MTC  
M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
MM74HC02MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
MM74HC02N  
N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code. (Tape and Reel not available in N14A.)  
Pb-Free package per JEDEC J-STD-020B.  
Connection Diagram  
Pin Assignment for DIP, SOIC, SOP and TSSOP  
Top View  
Logic Diagram  
© 2005 Fairchild Semiconductor Corporation  
DS005294  
www.fairchildsemi.com  

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