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MM74C165N PDF预览

MM74C165N

更新时间: 2024-11-01 12:46:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 移位寄存器
页数 文件大小 规格书
6页 64K
描述
Parallel-Load 8-Bit Shift Register

MM74C165N 数据手册

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October 1987  
Revised May 2002  
MM74C165  
Parallel-Load 8-Bit Shift Register  
General Description  
Features  
The MM74C165 functions as an 8-bit parallel-load, serial  
shift register. Data is loaded into the register independent  
of the state of the clock(s) when PARALLEL LOAD (PL) is  
low. Shifting is inhibited as long as PL is low. Data is  
sequentially shifted from complementary outputs, Q7 and  
Wide supply voltage range: 3V to 15V  
Guaranteed noise margin: 1V  
High noise immunity: 0.45 VCC (typ.)  
Low power TTL compatibility: fan out of 2 driving 74L  
Parallel loading independent of clock  
Dual clock inputs  
Q7, highest-order bit (P7) first. New serial data may be  
entered via the SERIAL DATA (Ds) input. Serial shifting  
occurs on the rising edge of CLOCK1 or CLOCK2. Clock  
inputs may be used separately or together for combined  
clocking from independent sources. Either clock input may  
be used also as an active-low clock enable. To prevent  
double-clocking when a clock input is used as an enable,  
the enable must be changed to a high level (disabled) only  
while the clock is HIGH.  
Fully static operation  
Ordering Code:  
Order Number Package Number  
Package Description  
MM74165N  
N16E  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Connection Diagram  
Top View  
© 2002 Fairchild Semiconductor Corporation  
DS005897  
www.fairchildsemi.com  

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