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MM74C175M PDF预览

MM74C175M

更新时间: 2024-01-12 03:02:51
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
6页 63K
描述
D Flip-Flop, CMOS Series, 1-Func, Positive Edge Triggered, 4-Bit, Complementary Output, CMOS, PDSO16, 0.150 INCH, MS-012, SOIC-16

MM74C175M 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.76
系列:CMOSJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:9.9 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:2000000 Hz最大I(ol):0.00036 A
位数:4功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5/15 V传播延迟(tpd):300 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:FF/Latches最大供电电压 (Vsup):15 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:3.9 mm
最小 fmax:5 MHzBase Number Matches:1

MM74C175M 数据手册

 浏览型号MM74C175M的Datasheet PDF文件第2页浏览型号MM74C175M的Datasheet PDF文件第3页浏览型号MM74C175M的Datasheet PDF文件第4页浏览型号MM74C175M的Datasheet PDF文件第5页浏览型号MM74C175M的Datasheet PDF文件第6页 
October 1987  
Revised May 2002  
MM74C175  
Quad D-Type Flip-Flop  
General Description  
Features  
The MM74C175 consists of four positive-edge triggered D-  
type flip-flops implemented with monolithic CMOS technol-  
ogy. Both are true and complemented outputs from each  
flip-flop are externally available. All four flip-flops are con-  
trolled by a common clock and a common clear. Informa-  
tion at the D-type inputs meeting the set-up time  
requirements is transferred to the Q outputs on the posi-  
tive-going edge of the clock pulse. The clearing operation,  
enabled by a negative pulse at Clear input, clears all four Q  
outputs to logical “0” and Q's to logical “1”.  
Wide supply voltage range: 3V to 15V  
Guaranteed noise margin: 1.0V  
High noise immunity: 0.45 VCC (typ.)  
Low power TTL compatibility: Fan out of 2 driving 74L  
All inputs are protected from static discharge by diode  
clamps to VCC and GND.  
Ordering Code:  
Order Number Package Number  
Package Description  
MM74C175M  
MM74C175N  
M16A  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Device also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.  
Connection Diagram  
Truth Table  
Each Flip-Flop  
Inputs  
Outputs  
Clear  
Clock  
D
X
H
L
Q
Q
H
L
H
H
H
H
X
L
H
L
L
H
H
L
X
X
NC  
NC  
NC  
NC  
H = HIGH Level  
L = LOW Level  
X = Irrelevant  
↑ = Transition from LOW-to-HIGH level  
NC = No Change  
Top View  
© 2002 Fairchild Semiconductor Corporation  
DS005900  
www.fairchildsemi.com  

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