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MM74C175N PDF预览

MM74C175N

更新时间: 2024-09-26 22:46:07
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 58K
描述
Quad D-Type Flip-Flop

MM74C175N 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.42
系列:CMOSJESD-30 代码:R-PDIP-T16
长度:19.305 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:2000000 Hz
最大I(ol):0.00036 A位数:4
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5/15 V
传播延迟(tpd):300 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:FF/Latches
最大供电电压 (Vsup):15 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:5 MHzBase Number Matches:1

MM74C175N 数据手册

 浏览型号MM74C175N的Datasheet PDF文件第2页浏览型号MM74C175N的Datasheet PDF文件第3页浏览型号MM74C175N的Datasheet PDF文件第4页浏览型号MM74C175N的Datasheet PDF文件第5页浏览型号MM74C175N的Datasheet PDF文件第6页 
October 1987  
Revised January 1999  
MM74C175  
Quad D-Type Flip-Flop  
All inputs are protected from static discharge by diode  
clamps to VCC and GND.  
General Description  
The MM74C175 consists of four positive-edge triggered D-  
type flip-flops implemented with monolithic CMOS technol-  
ogy. Both are true and complemented outputs from each  
flip-flop are externally available. All four flip-flops are con-  
trolled by a common clock and a common clear. Informa-  
tion at the D-type inputs meeting the set-up time  
requirements is transferred to the Q outputs on the posi-  
tive-going edge of the clock pulse. The clearing operation,  
enabled by a negative pulse at Clear input, clears all four Q  
outputs to logical “0” and Q's to logical “1”.  
Features  
Wide supply voltage range: 3V to 15V  
Guaranteed noise margin: 1.0V  
High noise immunity: 0.45 VCC (typ.)  
Low power TTL compatibility: Fan out of 2 driving 74L  
Ordering Code:  
Order Number Package Number  
Package Description  
MM74C175M  
M16A  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
MM74C175N  
N16E  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Connection Diagram  
Truth Table  
Each Flip-Flop  
Pin Assignments for DIP and SOIC  
Inputs  
Outputs  
Clear  
Clock  
D
X
H
L
Q
Q
H
L
H
H
H
H
X
L
H
L
L
H
H
L
X
X
NC  
NC  
NC  
NC  
H = HIGH Level  
L = LOW Level  
X = Irrelevant  
↑ = Transition from LOW-to-HIGH level  
NC = No Change  
Top View  
© 1999 Fairchild Semiconductor Corporation  
DS005900.prf  
www.fairchildsemi.com  

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