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MM74C165 PDF预览

MM74C165

更新时间: 2024-02-13 02:35:36
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 移位寄存器
页数 文件大小 规格书
6页 53K
描述
Parallel-Load 8-Bit Shift Register

MM74C165 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
风险等级:5.92JESD-30 代码:R-PDIP-T16
JESD-609代码:e0位数:8
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:3/15 V
认证状态:Not Qualified子类别:Shift Registers
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL

MM74C165 数据手册

 浏览型号MM74C165的Datasheet PDF文件第2页浏览型号MM74C165的Datasheet PDF文件第3页浏览型号MM74C165的Datasheet PDF文件第4页浏览型号MM74C165的Datasheet PDF文件第5页浏览型号MM74C165的Datasheet PDF文件第6页 
October 1987  
Revised January 1999  
MM74C165  
Parallel-Load 8-Bit Shift Register  
the enable must be changed to a high level (disabled) only  
while the clock is HIGH.  
General Description  
The MM74C165 functions as an 8-bit parallel-load, serial  
shift register. Data is loaded into the register independent  
of the state of the clock(s) when PARALLEL LOAD (PL) is  
low. Shifting is inhibited as long as PL is low. Data is  
sequentially shifted from complementary outputs, Q7 and  
Features  
Wide supply voltage range: 3V to 15V  
Guaranteed noise margin: 1V  
Q7, highest-order bit (P7) first. New serial data may be  
High noise immunity: 0.45 VCC (typ.)  
entered via the SERIAL DATA (Ds) input. Serial shifting  
occurs on the rising edge of CLOCK1 or CLOCK2. Clock  
inputs may be used separately or together for combined  
clocking from independent sources. Either clock input may  
be used also as an active-low clock enable. To prevent  
double-clocking when a clock input is used as an enable,  
Low power TTL compatibility: fan out of 2 driving 74L  
Parallel loading independent of clock  
Dual clock inputs  
Fully static operation  
Ordering Code:  
Order Number Package Number  
Package Description  
MM74165N  
N16E  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Connection Diagram  
Pin Assignments for DIP  
Top View  
© 1999 Fairchild Semiconductor Corporation  
DS005897.prf  
www.fairchildsemi.com  

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