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MM54HC76 PDF预览

MM54HC76

更新时间: 2024-09-15 22:46:11
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器
页数 文件大小 规格书
6页 138K
描述
Dual J-K Flip-Flops with Preset and Clear

MM54HC76 数据手册

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January 1988  
MM54HC76/MM74HC76 Dual J-K Flip-Flops  
with Preset and Clear  
General Description  
These high speed (30 MHz minimum) J-K Flip-Flops utilize  
advanced silicon-gate CMOS technology to achieve, the low  
power consumption and high noise immunity of standard  
CMOS integrated circuits, along with the ability to drive 10  
LS-TTL loads.  
The 54HC/74HC logic family is functionally as well as pin-  
out compatible with the standard 54LS/74LS logic family.  
All inputs are protected from damage due to static dis-  
charge by internal diode clamps to V  
and ground.  
CC  
Features  
Y
Each flip-flop has independent J, K, PRESET, CLEAR, and  
CLOCK inputs and Q and Q outputs. These devices are  
edge sensitive to the clock input and change state on the  
negative going transition of the clock pulse. Clear and pre-  
set are independent of the clock and accomplished by a low  
logic level on the corresponding input.  
Typical propagation delay: 16 ns  
Y
Wide operating voltage range  
Y
Low input current: 1 mA maximum  
Y
Low quiescent current: 40 mA maximum (74HC Series)  
Y
High output drive: 10 LS-TTL loads  
Connection and Logic Diagrams  
Truth Table  
Dual-In-Line Package  
Inputs  
CLK  
Outputs  
PR  
CLR  
J
L
Q
Q
L
H
L
H
L
X
X
X
X
X
L
X
X
X
L
H
L
L
H
L
X
L*  
Q0  
H
L*  
Q0  
L
H
H
H
H
H
H
H
H
H
H
v
v
v
v
H
H
L
L
H
H
X
L
H
H
X
TOGGLE  
Q0  
Q0  
*This is an unstable condition, and is not guaranteed  
TL/F/5074–1  
Top View  
Order Number MM54HC76 or MM74HC76  
TL/F/5074–3  
TL/F/5074–2  
(1 of 2)  
C
1995 National Semiconductor Corporation  
TL/F/5074  
RRD-B30M105/Printed in U. S. A.  

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