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MM54HC76J PDF预览

MM54HC76J

更新时间: 2024-11-08 22:46:11
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器
页数 文件大小 规格书
6页 138K
描述
Dual J-K Flip-Flops with Preset and Clear

MM54HC76J 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.92
其他特性:MASTER SLAVE OPERATION系列:HC/UH
JESD-30 代码:R-GDIP-T16JESD-609代码:e0
长度:19.43 mm负载电容(CL):50 pF
逻辑集成电路类型:J-K FLIP-FLOP位数:2
功能数量:2端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
传播延迟(tpd):37 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:NEGATIVE EDGE
宽度:7.62 mm最小 fmax:18 MHz
Base Number Matches:1

MM54HC76J 数据手册

 浏览型号MM54HC76J的Datasheet PDF文件第2页浏览型号MM54HC76J的Datasheet PDF文件第3页浏览型号MM54HC76J的Datasheet PDF文件第4页浏览型号MM54HC76J的Datasheet PDF文件第5页浏览型号MM54HC76J的Datasheet PDF文件第6页 
January 1988  
MM54HC76/MM74HC76 Dual J-K Flip-Flops  
with Preset and Clear  
General Description  
These high speed (30 MHz minimum) J-K Flip-Flops utilize  
advanced silicon-gate CMOS technology to achieve, the low  
power consumption and high noise immunity of standard  
CMOS integrated circuits, along with the ability to drive 10  
LS-TTL loads.  
The 54HC/74HC logic family is functionally as well as pin-  
out compatible with the standard 54LS/74LS logic family.  
All inputs are protected from damage due to static dis-  
charge by internal diode clamps to V  
and ground.  
CC  
Features  
Y
Each flip-flop has independent J, K, PRESET, CLEAR, and  
CLOCK inputs and Q and Q outputs. These devices are  
edge sensitive to the clock input and change state on the  
negative going transition of the clock pulse. Clear and pre-  
set are independent of the clock and accomplished by a low  
logic level on the corresponding input.  
Typical propagation delay: 16 ns  
Y
Wide operating voltage range  
Y
Low input current: 1 mA maximum  
Y
Low quiescent current: 40 mA maximum (74HC Series)  
Y
High output drive: 10 LS-TTL loads  
Connection and Logic Diagrams  
Truth Table  
Dual-In-Line Package  
Inputs  
CLK  
Outputs  
PR  
CLR  
J
L
Q
Q
L
H
L
H
L
X
X
X
X
X
L
X
X
X
L
H
L
L
H
L
X
L*  
Q0  
H
L*  
Q0  
L
H
H
H
H
H
H
H
H
H
H
v
v
v
v
H
H
L
L
H
H
X
L
H
H
X
TOGGLE  
Q0  
Q0  
*This is an unstable condition, and is not guaranteed  
TL/F/5074–1  
Top View  
Order Number MM54HC76 or MM74HC76  
TL/F/5074–3  
TL/F/5074–2  
(1 of 2)  
C
1995 National Semiconductor Corporation  
TL/F/5074  
RRD-B30M105/Printed in U. S. A.  

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