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MM54HC75J PDF预览

MM54HC75J

更新时间: 2024-11-05 22:46:11
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美国国家半导体 - NSC 触发器锁存器逻辑集成电路
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4页 144K
描述
4-Bit Bistable Latch with Q and Q Output

MM54HC75J 数据手册

 浏览型号MM54HC75J的Datasheet PDF文件第2页浏览型号MM54HC75J的Datasheet PDF文件第3页浏览型号MM54HC75J的Datasheet PDF文件第4页 
January 1988  
MM54HC75/MM74HC75  
4-Bit Bistable Latch with Q and Q Output  
General Description  
This 4-bit latch utilizes advanced silicon-gate CMOS tech-  
nology to achieve the high noise immunity and low power  
consumption normally associated with standard CMOS inte-  
grated circuits. These devices can drive 10 LS-TTL loads.  
The 54HC/74HC logic family is functionally as well as pin-  
out compatible with the standard 54LS/74LS logic family.  
All inputs are protected from damage due to static dis-  
charge by internal diode clamps to V  
and ground.  
CC  
This latch is ideally suited for use as temporary storage for  
binary information processing, input/output, and indicator  
units. Information present at the data (D) input is transferred  
to the Q output when the enable (G) is high. The Q output  
will follow the data input as long as the enable remains high.  
When the enable goes low, the information that was present  
at the data input at the time the transition occurred is re-  
tained at the Q output until the enable is permitted to go  
high again.  
Features  
Y
Typical operating frequency: 50 MHz  
Y
Y
Y
Y
Typical propagation delay: 12 ns  
Wide operating supply voltage range: 26V  
Low input current: 1 mA maximum  
Low quiescent supply current: 80 mA maximum  
(74HC Series)  
Y
Fanout of 10 LS-TTL loads  
Connection and Logic Diagrams  
Truth Table  
Dual-In-Line Package  
Inputs  
Outputs  
D
G
Q
Q
L
H
X
H
H
L
L
H
L
H
Q
Q
0
0
e
e
e
e
High Level: L Low Level  
H
X
Don’t Care  
Q
0
The level of Q before the transition of G  
TL/F/5303–1  
Order Number MM54HC75 or MM74HC75  
(1 of 4 latches)  
TL/F/5303–2  
C
1995 National Semiconductor Corporation  
TL/F/5303  
RRD-B30M105/Printed in U. S. A.  

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