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MH28D72KLG-75 PDF预览

MH28D72KLG-75

更新时间: 2024-10-26 22:30:11
品牌 Logo 应用领域
三菱 - MITSUBISHI 存储内存集成电路动态存储器双倍数据速率时钟
页数 文件大小 规格书
39页 336K
描述
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

MH28D72KLG-75 技术参数

生命周期:Obsolete零件包装代码:DIMM
包装说明:DIMM, DIMM184针数:184
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.36风险等级:5.43
Is Samacsys:N访问模式:DUAL BANK PAGE BURST
最长访问时间:0.75 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):133 MHzI/O 类型:COMMON
JESD-30 代码:R-XDMA-N184内存密度:9663676416 bit
内存集成电路类型:DDR DRAM MODULE内存宽度:72
功能数量:1端口数量:1
端子数量:184字数:134217728 words
字数代码:128000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128MX72输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:DIMM
封装等效代码:DIMM184封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY电源:2.5 V
认证状态:Not Qualified刷新周期:8192
自我刷新:YES子类别:DRAMs
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:NO LEAD端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

MH28D72KLG-75 数据手册

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Preliminary Spec.  
Some contents are subject to change without notice.  
MITSUBISHI LSIs  
MH28D72KLG-75,-10  
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module  
DESCRIPTION  
The MH28D72KLG is 134217728 - word x 72-bit Double  
Data Rate(DDR) Sy nchronous DRAM mounted module.  
This consists of 36 industry standard 64M x 4 DDR  
Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which  
achiev es v ery high speed data rate up to 133MHz.  
This socket-ty pe memory module is suitable f or main  
memory in computer systems and easy to interchange or  
add modules.  
93pin  
1pin  
FEATURES  
CLK  
Max.  
Access Time  
[component level]  
Type name  
Frequency  
+ 0.75ns  
MH28D72KLG-75  
MH28D72KLG-10  
133MHz  
100MHz  
+ 0.8ns  
144pin  
145pin  
52pin  
53pin  
- Utilizes industry standard 64M X 4 DDR Synchronous DRAMs  
in TSOP package , industry standard Registered Buffer in  
TSSOP package , and industry standard PLL in TSSOP package.  
- Vdd=Vddq=2.5v ±0.2V  
- Double data rate architecture; two data transf ers per  
clock cycle  
- Bidirectional, data strobe (DQS) is transmitted/receiv ed  
with data  
- Dif f erential clock inputs (CLK and /CLK)  
- data ref erenced to both edges of DQS  
- /CAS latency - 2.0/2.5 (programmable)  
- Burst length- 2/4/8 (programmable)  
- Auto precharge / All bank precharge controlled by A10  
- 8192 ref resh cycles /64ms  
- Auto ref resh and Self ref resh  
- Row address A0-12 / Column address A0-9,11  
- SSTL_2 Interf ace  
184pin  
92pin  
- Module 2bank Conf igration  
- Burst Ty pe - sequential/interleav e(programmable)  
- Commands entered on each positiv e CLK edge  
APPLICATION  
Main memory unit for PC, PC server, Server, W S.  
MIT-DS-0412-0.1  
21.Mar.2001  
MITSUBISHI ELECTRIC  
1

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