MD3872
Supertex inc.
Low Power, Low Noise Ultrasound Receive Front-End
Eight-Channels of LNA, VGA, AAF, CPS & 12-Bit, 50MHz ADCs
Features
General Description
► 1.8V Analog/Digital supply
The MD3872 is an eight-channel front-end receiver for medical
ultrasound imaging. Its excellent low power dynamic performance
is especially suitable for portable ultrasound applications.
► 3.3V supply for CW Doppler output bias
► Fully differential inputs and outputs
► SPI programmable LNA gain = 14dB/18dB
► LNA input range 480mVPP/300mVPP
► Dual mode active input impedance matching
► 1.1nV/√Hz Input Voltage Noise at 5.0MHz
► 1.0pA/√Hz Input Current Noise at 5.0MHz
► 0 to -47dB Linear-in-dB variable Gain of VCA
► 4 PGA Gain settings: 23.5, 29.0, 34.5 & 40.0dB
► Third Order Anti-Aliasing Filter (AAF)
► Program/Auto-tracking AAF (6.6~15MHz)
► Integrated 8×8 Cross-Point Switch (CPS)
► SNR 66dB, SFDR 74dB for ADC
The circuit of each channel is composed of a 14dB/18dB low
noise pre-amplifier (LNA), a voltage- controlled attenuator (VCA
or TGC), a programmable gain amplifier (PGA), an anti-aliasing
filter (AAF) and an analog-to-digital (ADC) converter. The gain
and gain range of the VGA can be digitally configured separately.
The gain of the PGA can be set to one of four discrete values:
23.5dB, 29dB, 34.5dB or 40dB. The VCA can be continuously
varied by a control voltage from -47dB to a maximum of 0dB.
In CW mode, an integrated trans-conductance amplifier is driven
by the LNA to generate differential output current. The resulting
signal currents of each channel then connect to an 8×8 differential
cross-point switch which can be programmed through the SPI.
► Built-in reference voltage
► LVDS per ANSI-644
► Fast overload recovery time
► Low power 95mW/ch, 50mW/ch CW
The 12-bit ADC is based on a pipeline structure to provide high
static linearity. The data, clock, and frame alignment signal
outputs are serial LVDS in binary format for each channel.
Applications
► Medical ultrasound imaging
► Portable ultrasound instrumentation
► Transducer signal processing
Block Diagram
CWVDD (+3.3V)
AVDD (+1.8V)
PLL
DVDD (+1.8V)
CLK+
CLK-
FLEX
+
-
6 X CLK
CWX+
CWX-
FCLK+
FCLK-
SW1
PA1-
+
LNA
-
IN1+
OUT1+
OUT1-
ADC
VGA
VGA
AAF
AAF
12bits
IN1-
SW2
PA2-
+
LNA
-
Data
Ser. &
LVDS
IN2+
IN2-
OUT2+
OUT2-
ADC
12bits
SW8
PA8-
OUT8+
OUT8-
EBC
+
LNA
-
IN8+
IN8-
ADC
12bits
VGA
AAF
RBIAS
CSB
CM0-8
SPI
Reference
CW-SW
9
PDWN
STBY
16
DGND
CW1-8
TGC GSC
VREF
EXT
REF+ REF-
SCK SDI SDO
Doc.# DSFP-MD3872
B060413
Supertex inc.
www.supertex.com