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MCM69P817ZP3 PDF预览

MCM69P817ZP3

更新时间: 2024-11-10 22:23:39
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 存储静态存储器
页数 文件大小 规格书
16页 181K
描述
256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

MCM69P817ZP3 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:BGA,Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.92Is Samacsys:N
Base Number Matches:1

MCM69P817ZP3 数据手册

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Order this document  
by MCM69P817/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM69P817  
Product Preview  
256K x 18 Bit Pipelined  
BurstRAM Synchronous  
Fast Static RAM  
The MCM69P817 is a 4M bit synchronous fast static RAM designed to provide  
a burstable, high performance, secondary cache for the PowerPC and other  
high performance microprocessors. It is organized as 256K words of 18 bits  
each. This device integrates input registers, an output register, a 2–bit address  
counter, andahighspeedSRAMontoasinglemonolithiccircuitforreducedparts  
count in cache data RAM applications. Synchronous design allows precise cycle  
control with the use of an external clock (K).  
ZP PACKAGE  
PBGA  
CASE 999–01  
Addresses (SA), data inputs (DQx), and all control signals except output  
enable(G) and linear burst order (LBO) are clock (K) controlled through positive–  
edge–triggered noninverting registers.  
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst  
addresses can be generated internally by the MCM69P817 (burst sequence  
operates in linear or interleaved mode dependent upon the state of LBO) and  
controlled by the burst address advance (ADV) input pin.  
Write cycles are internally self–timed and are initiated by the rising edge of the  
clock (K) input. This feature eliminates complex off–chip write pulse generation  
and provides increased timing flexibility for incoming signals.  
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-  
nous write enable (SW) are provided to allow writes to either individual bytes or  
to all bytes. The two bytes are designated as “a” and “b”. SBa controls DQa and  
SBb controls DQb. Individual bytes are written if the selected byte writes SBx are  
asserted with SW. All bytes are written if either SGW is asserted or if all SBx and  
SW are asserted.  
For read cycles, pipelined SRAMs output data is temporarily stored by an  
edge–triggeredoutput register and then released to the output buffers at the next  
rising edge of clock (K).  
The MCM69P817 operates from a 3.3 V core power supply and all outputs  
operate on a 3.3 V or 2.5 V power supply. All inputs and outputs are JEDEC stan-  
dard JESD8–5 compatible.  
MCM69P817 Speed Options  
Pipelined  
t
Speed  
t
Setup  
0.5 ns  
0.5 ns  
0.5 ns  
Hold  
1 ns  
1 ns  
1 ns  
I
Pkg  
KHQV  
KHKH  
DD  
200 MHz  
180 MHz  
166 MHz  
5 ns  
2.5 ns  
3.0 ns  
3.5 ns  
475 mA  
450 mA  
425 mA  
PBGA  
PBGA  
PBGA  
5.5 ns  
6 ns  
3.3 V + 10%, – 5% Core Power Supply, Operates with a 3.3 V or 2.5 V I/O  
Supply  
ADSP, ADSC, and ADV Burst Control Pins  
Selectable Burst Sequencing Order (Linear/Interleaved)  
Single–Cycle Deselect Timing  
Internally Self–Timed Write Cycle  
Byte Write and Global Write Control  
PB1 Version 2.0 Compatible  
JEDEC Standard 119–Pin PBGA Package  
BurstRAM is a trademark of Motorola, Inc.  
The PowerPC name is a trademark of IBM Corp., used under license therefrom.  
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.  
6/10/97  
Motorola, Inc. 1997  

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