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MCM6264CP20 PDF预览

MCM6264CP20

更新时间: 2024-02-16 10:35:25
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
8页 181K
描述
8K x 8 Bit Fast Static RAM

MCM6264CP20 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP28,.3针数:28
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.81
最长访问时间:20 nsI/O 类型:COMMON
JESD-30 代码:R-PDIP-T28JESD-609代码:e0
长度:34.67 mm内存密度:65536 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
功能数量:1端口数量:1
端子数量:28字数:8192 words
字数代码:8000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:8KX8输出特性:3-STATE
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP28,.3
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
座面最大高度:4.57 mm最大待机电流:0.02 A
最小待机电流:4.5 V子类别:SRAMs
最大压摆率:0.13 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

MCM6264CP20 数据手册

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Order this document  
by MCM6264C/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM6264C  
8K x 8 Bit Fast Static RAM  
TheMCM6264CisfabricatedusingMotorola’shigh–performancesilicon–gate  
CMOS technology. Static design eliminates the need for external clocks or timing  
strobes, while CMOS circuitry reduces power consumption and provides for  
greater reliability.  
This device meets JEDEC standards for functionality and pinout, and is avail-  
able in plastic dual–in–line and plastic small–outline J–leaded packages.  
P PACKAGE  
300 MIL PLASTIC  
CASE 710B–01  
Single 5 V ± 10% Power Supply  
Fully Static — No Clock or Timing Strobes Necessary  
Fast Access Times: 12, 15, 20, 25, and 35 ns  
Equal Address and Chip Enable Access Times  
Output Enable (G) Feature for Increased System Flexibility and to  
Eliminate Bus Contention Problems  
J PACKAGE  
300 MIL SOJ  
CASE 810B–03  
Low Power Operation: 110 – 150 mA Maximum AC  
Fully TTL Compatible — Three State Output  
PIN ASSIGNMENT  
NC  
1
2
3
4
5
6
7
8
9
10  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
V
CC  
BLOCK DIAGRAM  
A12  
W
A7  
A6  
A5  
A4  
A3  
A2  
A1  
E2  
A8  
A9  
A11  
A2  
V
V
A3  
CC  
SS  
A4  
A5  
MEMORY MATRIX  
256 ROWS x 32  
x 9 COLUMNS  
G
ROW  
DECODER  
A7  
A10  
E1  
A8  
A0  
DQ7  
DQ6  
DQ5  
DQ4  
A9  
DQ0  
11  
12  
18  
17  
A11  
DQ1  
DQ2  
DQ0  
13  
14  
16  
15  
COLUMN I/O  
INPUT  
DATA  
CONTROL  
COLUMN DECODER  
V
DQ3  
SS  
DQ7  
A0 A1 A6 A10 A12  
PIN NAMES  
A0 – A12 . . . . . . . . . . . . . Address Input  
DQ0 – DQ7 . . . Data Input/Data Output  
W . . . . . . . . . . . . . . . . . . . . Write Enable  
G . . . . . . . . . . . . . . . . . . . Output Enable  
E1, E2 . . . . . . . . . . . . . . . . . Chip Enable  
E1  
E2  
W
G
V
CC  
V
SS  
. . . . . . . . . . . Power Supply (+ 5 V)  
. . . . . . . . . . . . . . . . . . . . . . . Ground  
REV 2  
5/95  
Motorola, Inc. 1995  

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