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MCM6265C

更新时间: 2024-10-31 22:54:51
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
8页 181K
描述
8K x 9 Bit Fast Static RAM

MCM6265C 数据手册

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Order this document  
by MCM6265C/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM6265C  
8K x 9 Bit Fast Static RAM  
TheMCM6265CisfabricatedusingMotorola’shigh–performancesilicon–gate  
CMOS technology. Static design eliminates the need for external clocks or timing  
strobes, while CMOS circuitry reduces power consumption and provides for  
greater reliability.  
This device meets JEDEC standards for functionality and pinout, and is avail-  
able in plastic dual–in–line and plastic small–outline J–leaded packages.  
P PACKAGE  
300 MIL PLASTIC  
CASE 710B–01  
Single 5 V ± 10% Power Supply  
Fully Static — No Clock or Timing Strobes Necessary  
Fast Access Times: 12, 15, 20, 25, and 35 ns  
Equal Address and Chip Enable Access Times  
Output Enable (G) Feature for Increased System Flexibility and to  
Eliminate Bus Contention Problems  
J PACKAGE  
300 MIL SOJ  
CASE 810B–03  
Low Power Operation: 110 – 150 mA Maximum AC  
Fully TTL Compatible — Three State Output  
PIN ASSIGNMENT  
A8  
A7  
1
2
3
4
5
6
7
8
9
10  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
V
CC  
BLOCK DIAGRAM  
W
A6  
A5  
A4  
A3  
A2  
A1  
A0  
E2  
A2  
A9  
V
V
A3  
CC  
SS  
A10  
A11  
A4  
A5  
MEMORY MATRIX  
256 ROWS x 32  
x 9 COLUMNS  
G
ROW  
DECODER  
A7  
A12  
E1  
A9  
DQ0  
DQ1  
DQ8  
DQ7  
DQ6  
DQ5  
A10  
A11  
11  
12  
18  
17  
DQ2  
DQ3  
DQ0  
13  
14  
16  
15  
COLUMN I/O  
INPUT  
DATA  
CONTROL  
COLUMN DECODER  
V
DQ4  
SS  
DQ8  
A0 A1 A6 A8 A12  
PIN NAMES  
A0 – A12 . . . . . . . . . . . . . Address Input  
DQ0 – DQ8 . . . Data Input/Data Output  
W . . . . . . . . . . . . . . . . . . . . Write Enable  
G . . . . . . . . . . . . . . . . . . . Output Enable  
E1, E2 . . . . . . . . . . . . . . . . . Chip Enable  
E1  
E2  
W
G
V
CC  
V
SS  
. . . . . . . . . . . Power Supply (+ 5 V)  
. . . . . . . . . . . . . . . . . . . . . . . Ground  
REV 2  
5/95  
Motorola, Inc. 1994  

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