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MC92500

更新时间: 2024-11-12 22:46:19
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摩托罗拉 - MOTOROLA 异步传输模式ATM
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描述
ATM Cell Processor

MC92500 数据手册

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Order this document by MC92500/D  
MOTOROLA  
SEMICONDUCTOR TECHNICAL DATA  
ΤΜ  
ATM Cell Processor  
The ATM Cell Processor (MC92500) is a peripheral device composed of dedicated  
high performance Ingress and Egress Cell Processors combined with UTOPIA  
Compliant PHY and Switch Interface ports (see Figure 1).  
MC92500  
ATM Cell Processor  
MC92500 Features  
Full duplex operation at SONET STS-3c, SONET STS-1, DS3 PLCP, or any physical link  
running up to 155 Mbit/sec  
Implements ATM Layer functions for broadband ISDN according to ITU recommendations  
and ATM forum UNI specification  
Performs internal VPI and VCI address compression (with an option for external  
compression) for up to 64K VCs  
Supports up to 16 physical links using dedicated Ingress/Egress MultiPhy control signals  
Each physical link can be configured as either a UNI or NNI port  
Supports multicast, multiport address translation  
Maintains both virtual connection and physical link counters on both Ingress and Egress  
cell flows for detailed billing and diagnostics  
ZQ SUFFIX  
GTBGA  
CASE 5203  
Provides a flexible 32 bit external memory port for context management  
Automated AIS, RDI, CC and Loopback functions with Performance Monitoring Block Test  
on up to 64 Bidirectional connections  
Ordering Information  
Programmable 32 bit microprocessor interface supporting either big- or little-endian bus  
formats  
Device  
Package  
Per-connection leaky-bucket based UPC or NPC design with up to four buckets per  
connection allows any combination of CLP-aware peak, average, and burst-length  
policing with programmable tag/drop action per policer  
MC92500ZQ 256 GTBGA  
Implements separate rate controlled cell insertion and priority based cell extraction  
queues accessible from all cell flows  
Supports a programmable number of additional switch overhead parameters allowing  
adaptation to any switch routing header format  
Utopia  
I/F  
Utopia  
I/F  
Ingress Switch I/F  
(ISWI)  
Ingress PHY I/F (IPHI)  
MultiPhy Support  
Ingress Cell Processor  
(IPU)  
Memory  
I/F  
External Memory I/F  
(EMIF)  
Host  
System  
Microprocessor I/F  
(MPIF)  
JTAG  
Boundary  
Scan  
Test  
Port  
FMC Generation  
(FMC)  
Internal SCAN  
(ISCAN)  
Utopia  
I/F  
Utopia  
I/F  
Egress PHY I/F (EPHI)  
MultiPhy Support  
Egress Switch I/F  
(ESWI)  
Egress Cell Processor  
(EPU)  
Figure 1. Representative Block Diagram  
This document contains information on a new product. Specifications and information herein are subject to change  
without notice.  
MOTOROLA, INC. 1997  
REV 1.1  

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