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MC92500ZQ PDF预览

MC92500ZQ

更新时间: 2024-01-19 19:18:59
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
页数 文件大小 规格书
42页 265K
描述
ATM Cell Processor

MC92500ZQ 技术参数

生命周期:Transferred零件包装代码:BGA
包装说明:BGA,针数:256
Reach Compliance Code:unknownECCN代码:5A991
HTS代码:8542.31.00.01风险等级:5.44
JESD-30 代码:S-PBGA-B256长度:27 mm
功能数量:1端子数量:256
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装形状:SQUARE封装形式:GRID ARRAY
认证状态:Not Qualified座面最大高度:2.43 mm
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:ATM/SONET/SDH NETWORK INTERFACE温度等级:COMMERCIAL
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM宽度:27 mm
Base Number Matches:1

MC92500ZQ 数据手册

 浏览型号MC92500ZQ的Datasheet PDF文件第2页浏览型号MC92500ZQ的Datasheet PDF文件第3页浏览型号MC92500ZQ的Datasheet PDF文件第4页浏览型号MC92500ZQ的Datasheet PDF文件第5页浏览型号MC92500ZQ的Datasheet PDF文件第6页浏览型号MC92500ZQ的Datasheet PDF文件第7页 
Order this document by MC92500/D  
MOTOROLA  
SEMICONDUCTOR TECHNICAL DATA  
ΤΜ  
ATM Cell Processor  
The ATM Cell Processor (MC92500) is a peripheral device composed of dedicated  
high performance Ingress and Egress Cell Processors combined with UTOPIA  
Compliant PHY and Switch Interface ports (see Figure 1).  
MC92500  
ATM Cell Processor  
MC92500 Features  
Full duplex operation at SONET STS-3c, SONET STS-1, DS3 PLCP, or any physical link  
running up to 155 Mbit/sec  
Implements ATM Layer functions for broadband ISDN according to ITU recommendations  
and ATM forum UNI specification  
Performs internal VPI and VCI address compression (with an option for external  
compression) for up to 64K VCs  
Supports up to 16 physical links using dedicated Ingress/Egress MultiPhy control signals  
Each physical link can be configured as either a UNI or NNI port  
Supports multicast, multiport address translation  
Maintains both virtual connection and physical link counters on both Ingress and Egress  
cell flows for detailed billing and diagnostics  
ZQ SUFFIX  
GTBGA  
CASE 5203  
Provides a flexible 32 bit external memory port for context management  
Automated AIS, RDI, CC and Loopback functions with Performance Monitoring Block Test  
on up to 64 Bidirectional connections  
Ordering Information  
Programmable 32 bit microprocessor interface supporting either big- or little-endian bus  
formats  
Device  
Package  
Per-connection leaky-bucket based UPC or NPC design with up to four buckets per  
connection allows any combination of CLP-aware peak, average, and burst-length  
policing with programmable tag/drop action per policer  
MC92500ZQ 256 GTBGA  
Implements separate rate controlled cell insertion and priority based cell extraction  
queues accessible from all cell flows  
Supports a programmable number of additional switch overhead parameters allowing  
adaptation to any switch routing header format  
Utopia  
I/F  
Utopia  
I/F  
Ingress Switch I/F  
(ISWI)  
Ingress PHY I/F (IPHI)  
MultiPhy Support  
Ingress Cell Processor  
(IPU)  
Memory  
I/F  
External Memory I/F  
(EMIF)  
Host  
System  
Microprocessor I/F  
(MPIF)  
JTAG  
Boundary  
Scan  
Test  
Port  
FMC Generation  
(FMC)  
Internal SCAN  
(ISCAN)  
Utopia  
I/F  
Utopia  
I/F  
Egress PHY I/F (EPHI)  
MultiPhy Support  
Egress Switch I/F  
(ESWI)  
Egress Cell Processor  
(EPU)  
Figure 1. Representative Block Diagram  
This document contains information on a new product. Specifications and information herein are subject to change  
without notice.  
MOTOROLA, INC. 1997  
REV 1.1  

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