Datasheet > MC92303

MC92303

更新时间： 2024-11-24 12:46:39

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		/
页数	文件大小	规格书
3页	37K
描述
QPSK/BPSK DIGITAL DEMODULATOR

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中文翻译

获取价格

数据手册

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MC92303 数据手册

Current Information@www.mot.com/ADC

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MC92303

Product Brief

QPSK/BPSK DIGITAL DEMODULATOR

CLK

RESET

I,Q[5:0]

The MC92303 is a coherent digital demodulator for QPSK and BPSK modulated

signals utilized in Digital-TV applications according to the EBU defined DVB transmis-

sion standard for satellite Set-Top systems or similar. The MC92303 contains all the

functionality required to lock onto signals with frequency offsets as large as the baud

rate and extract the desired signal from a frequency band with adjacent channel inter-

ference and other undesirable signals.

VCO

AGC

CLK_VCO

FORMAT

Q_soft[2:0]

I_soft[2:0]

SDA

SADR[6:0]

SCL

Feature Summary

•

DVB compliant QPSK/BPSK Coherent Demodulator

Variable Modulation Rate up to 30 MBaud to work with all present European DVB

Channels

•

Selectable Input Format (Offset Binary/2’s Complement)

DC Offset Removal, I/Q-swapping and Input Format Selection in one block

Decimation Filters for Oversampling Ratios of 2/T, 3/T, 4/T, 6/T, 8/T, 12/T and 16/T

Half Nyquist Baseband Filters (α=0.35)

Ordering Information

Device

Package

Internal Numerically Controlled Oscillator (NCO)

MC92303BT

160QFP

Automatic Gain Control (AGC) provided to analog front-end

Automatic Frequency Control (AFC) to ±Rs (Symbol Rate)

Clock Synchronization with 1-Bit Σ∆-Converter Output for ADC control

Programmable Second Order Loop Filters for Carrier Recovery and AGC

3-bit Soft Decision output per Symbol with selectable format (Offset Binary/2’s

Complement/Sign Magnitude)

•

Programmable Sampling Rates of the Digital Sigma-Delta Converters

< 0.5 dB Implementation Loss from theory

I C Programmable Interface

0.5µ CMOS Process at 3.3V

AGC

Loop Filter

AFC / Clock

Synchron.

Ext. Clkref.

VCO

Control

AGC

Control

Σ∆

DC-

Removal

I_soft

Q_soft

Decimation

Filter

Complex

Multiplier

Half Nyquist

Filter

8/3 Bit Mapper

Data

Estimator

Digital AGC

cosΘ

sinΘ

SDA

SCL

False Lock Detector

Phase Lock Detector

I²C

Interface

Sweep /

Carrier

Loop Filter

NCO

SADR

Parameters

Figure 1. QPSK/BPSK Demodulator Block Diagram

This document contains information on a new product.

Speciﬁcations and information herein are subject to change without notice.

MOTOROLA, INC. 1997

4/10/97

12 3

中文翻译

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