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MC92460ZU PDF预览

MC92460ZU

更新时间: 2024-09-25 20:01:31
品牌 Logo 应用领域
恩智浦 - NXP 通信时钟数据传输外围集成电路
页数 文件大小 规格书
2页 200K
描述
MULTICHNL HDLC CNTRL

MC92460ZU 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Transferred零件包装代码:BGA
包装说明:LBGA, PGA480,29X29,50针数:480
Reach Compliance Code:not_compliantECCN代码:5A991.G
HTS代码:8542.31.00.01风险等级:5.78
地址总线宽度:32边界扫描:YES
总线兼容性:60X最大时钟频率:16 MHz
通信协议:SYNC, HDLC最大数据传输速率:8.3375 MBps
外部数据总线宽度:64JESD-30 代码:S-PBGA-B480
JESD-609代码:e0长度:37.5 mm
湿度敏感等级:4串行 I/O 数:40
端子数量:480最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装等效代码:PGA480,29X29,50
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE
峰值回流温度(摄氏度):220电源:2,3.3 V
认证状态:Not Qualified座面最大高度:1.65 mm
子类别:Serial IO/Communication Controllers最大供电电压:1.95 V
最小供电电压:1.65 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:37.5 mmuPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches:1

MC92460ZU 数据手册

 浏览型号MC92460ZU的Datasheet PDF文件第2页 
igabit Ethernet SerDes Transceiver  
MC92604  
MC92604 DUAL GIGABIT ETHERNET TRANSCEIVER BLOCK DIAGRAM  
The MC92604 Dual Gigabit Ethernet transceiver  
is a 1.25 giga-baud, full-duplex, interface device  
that can be used to transmit data between chips  
across a board, through a backplane, or through  
cabling, as well as to interface to GBIC/SFP  
modules. It was designed with the intent to meet  
(As a single with redundancy, only channel A is used.)  
Two Transceivers x = A & B  
8B10B  
XMIT_x_ENABLE  
Decoder  
XMIT_x_DATA [7:0]  
XLINK_x_N  
XLINK_x_P  
MEDIA  
BIST  
FIFO  
Transmitter  
XMIT_x_K/ERR  
®
XMIT_x_CLK  
the requirements of IEEE Std. 802.3-2002 .  
XCVR_x_DISABLE  
XCVR_x_LBE  
8B10B  
Decoder  
RECV_x_DATA [7:0]  
RECV_x_K  
The MC92604 is two parts in one. It may be  
configured as either a dual channel 1 gigabit  
backplane serializer/deserializer, SerDes, or it is  
a dual 1 gigabit GMII or TBI PHY for Ethernet  
1000Base-X applications. The dual MC92604  
may optionally be configured as a single channel  
transceiver with serial link redundancy. The device  
fully supports the MDIO interface defined in the  
above referenced standard.  
RLINK_x_P  
RLINK_x_N  
Receive  
Interface  
Unit  
6
FIFO  
RECV_x_ERR  
RECV_x_DV  
Receiver  
RECV_x_CLK  
RECV_x_CLK_B  
CLK  
GEN  
REF_CLK  
System  
PLL  
RESET  
REF_CLK_B  
CONFIG_INPUTS  
LINK CONTROLLER  
2
CLK_OUT__[1:0]  
MD_DATA  
MD_CLK  
3
TDI, TRST_B, TCK  
TDO  
MDIO  
CONTOLLER  
JTAG  
CONTROLLER  
MD_ADR [4:2]  
MD_ENABLE  
The MC92604 features transmit FIFOs and  
source-synchronous transmit clocks per channel  
to further simplify interfacing that will support  
many other non-Ethernet applications. And finally,  
IEEE Std 1149.1 JTAG boundary scan is added  
for board test support.  
Typical applications  
> High-density board applications for  
communications designs utilizing  
IEEE 802.3 protocol  
The Gigabit Ethernet transceiver is carefully  
designed for low power consumption and is built  
upon the proven transceiver technology in the  
MC92600 and MC92602 Quad SerDes devices.  
The MC92604 transceiver is offered in a JEDEC  
standard 196 pin 15 mm body size package  
to provide excellent board density in applications  
with a large number of channels.  
> High-speed data transfer applications in  
high-bandwidth backplane and chassis-to-  
chassis networking  
> PHY interface to Motorola C-port  
(C-3e or C-5e) network processors and  
Power QUICC III (MPC8560 or MPC8540)  
communications processors  

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