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MC74VHCT259AMEL PDF预览

MC74VHCT259AMEL

更新时间: 2024-11-04 05:22:07
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9页 116K
描述
8−Bit Addressable Latch/1−of−8 Decoder CMOS Logic Level Shifter with LSTTL−Compatible Inputs

MC74VHCT259AMEL 数据手册

 浏览型号MC74VHCT259AMEL的Datasheet PDF文件第2页浏览型号MC74VHCT259AMEL的Datasheet PDF文件第3页浏览型号MC74VHCT259AMEL的Datasheet PDF文件第4页浏览型号MC74VHCT259AMEL的Datasheet PDF文件第5页浏览型号MC74VHCT259AMEL的Datasheet PDF文件第6页浏览型号MC74VHCT259AMEL的Datasheet PDF文件第7页 
MC74VHCT259A  
8−Bit Addressable  
Latch/1−of−8 Decoder  
CMOS Logic Level Shifter  
with LSTTL−Compatible Inputs  
http://onsemi.com  
MARKING  
The MC74VHCT259 is an 8−bit Addressable Latch fabricated with  
silicon gate CMOS technology. It achieves high speed operation  
similar to equivalent Bipolar Schottky TTL while maintaining CMOS  
low power dissipation.  
DIAGRAMS  
16  
1
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output.  
The VHC259 is designed for general purpose storage applications in  
digital systems. The device has four modes of operation as shown in  
the mode selection table. In the addressable latch mode, the signal on  
Data In is written into the addressed latch. The addressed latch follows  
the data input with all non−addressed latches remaining in their  
previous states. In the memory mode, all latches remain in their  
previous state and are unaffected by the Data or Address inputs. In the  
one−of−eightdecoding or demultiplexing mode, the addressed output  
follows the state of Data In with all other outputs in the LOW state. In  
the Reset mode, all outputs are LOW and unaffected by the address  
and data inputs. When operating the VHCT259 as an addressable  
latch, changing more than one bit of the address could impose a  
transient wrong address. Therefore, this should only be done while in  
the memory mode.  
SOIC−16  
D SUFFIX  
CASE 751B  
VHCT259AG  
AWLYWW  
1
16  
VHCT  
259A  
ALYWG  
G
TSSOP−16  
DT SUFFIX  
CASE 948F  
1
1
16  
SOEIAJ−16  
M SUFFIX  
CASE 966  
74VHCT259  
ALYWG  
The VHCT inputs are compatible with TTL levels. This device can  
be used as a level converter for interfacing 3.3 V to 5.0 V because it  
has full 5.0 V CMOS level output swings.  
1
1
The VHCT259A input structures provide protection when voltages  
between 0 V and 5.5 V are applied, regardless of the supply voltage.  
A
WL, L  
Y
= Assembly Location  
= Wafer Lot  
= Year  
The output structures also provide protection when V = 0 V. These  
CC  
WW, W = Work Week  
input and output structures help prevent device destruction caused by  
supply voltage−input/output voltage mismatch, battery backup, hot  
insertion, etc.  
G or G  
= Pb−Free Package  
(Note: Microdot may be in either location)  
Features  
ORDERING INFORMATION  
High Speed: t = 7.6 ns (Typ) at V = 5.0 V  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
PD  
CC  
Low Power Dissipation: I = 2 mA (Max) at T = 25°C  
CC  
A
TTL−Compatible Inputs: V = 0.8 V; V = 2.0 V  
IL  
IH  
Power Down Protection Provided on Inputs and Outputs  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300 mA  
ESD Performance: HBM > 2000 V  
Pb−Free Packages are Available*  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
January, 2006 − Rev. 4  
MC74VHCT259A/D  

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