SEMICONDUCTOR TECHNICAL DATA
The MC74VHCT540A is an advanced high speed CMOS inverting octal
bus buffer fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The MC74VHCT540A features inputs and outputs on opposite sides of the
package and two AND–ed active–low output enables. When either OE1 or
OE2 are high, the terminal outputs are in the high impedance state.
The VHCT inputs are compatible with TTL levels. This device can be used
as a level converter for interfacing 3.3V to 5.0V, because it has full 5V CMOS
level output swings.
DW SUFFIX
20–LEAD SOIC WIDE PACKAGE
CASE 751D–05
The VHCT540A input and output (when disabled) structures provide
protection when voltages between 0V and 5.5V are applied, regardless of
the supply voltage. These input and output structures help prevent device
destruction caused by supply voltage – input/output voltage mismatch,
battery backup, hot insertion, etc.
DT SUFFIX
20–LEAD TSSOP PACKAGE
CASE 948E–02
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
M SUFFIX
20–LEAD SOIC EIAJ PACKAGE
CASE 967–01
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•
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•
•
•
•
•
•
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•
High Speed: t
= 3.7ns (Typ) at V
= 5V
PD
Low Power Dissipation: I
CC
= 4µA (Max) at T = 25°C
CC
A
ORDERING INFORMATION
TTL–Compatible Inputs: V = 0.8V; V = 2.0V
Power Down Protection Provided on Inputs
Balanced Propagation Delays
IL IH
MC74VHCTXXXADW SOIC WIDE
MC74VHCTXXXADT
MC74VHCTXXXAM
TSSOP
SOIC EIAJ
Designed for 2V to 5.5V Operating Range
Low Noise: V
= 1.2V (Max)
OLP
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
Chip Complexity: 124 FETs or 31 Equivalent Gates
PIN ASSIGNMENT
OE1
1
20
V
CC
A1
A2
A3
2
3
4
19
18
17
OE2
Y1
LOGIC DIAGRAM
Y2
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
A1
A2
A3
A4
A5
A6
A7
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
A4
A5
5
16
15
14
13
12
11
Y3
Y4
Y5
Y6
Y7
Y8
6
A6
7
A7
8
A8
9
DATA
INPUTS
INVERTING
OUTPUTS
GND
10
FUNCTION TABLE
Inputs
Output Y
OE1
OE2
A
L
L
H
X
L
L
X
H
L
H
X
X
H
L
Z
Z
A8
1
OE1
OUTPUT
ENABLES
19
OE2
4/99
REV 0
1
Motorola, Inc. 1999