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MC74VHC574MR2 PDF预览

MC74VHC574MR2

更新时间： 2024-11-05 14:53:15
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
8页 137K
描述
AHC/VHC SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, EIAJ, SOIC-20

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中文翻译

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MC74VHC574MR2 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP,
针数：20Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.23
系列：AHC/VHCJESD-30 代码：R-PDSO-G20
JESD-609代码：e0长度：12.575 mm
逻辑集成电路类型：BUS DRIVER位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
传播延迟（tpd）：19 ns认证状态：Not Qualified
座面最大高度：2.05 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：5.275 mmBase Number Matches：1

MC74VHC574MR2 数据手册

 浏览型号MC74VHC574MR2的Datasheet PDF文件第2页浏览型号MC74VHC574MR2的Datasheet PDF文件第3页浏览型号MC74VHC574MR2的Datasheet PDF文件第4页浏览型号MC74VHC574MR2的Datasheet PDF文件第5页浏览型号MC74VHC574MR2的Datasheet PDF文件第6页浏览型号MC74VHC574MR2的Datasheet PDF文件第7页 
MC74VHC574  
Octal D-Type Flip-Flop  
with 3-State Output  
The MC74VHC574 is an advanced high speed CMOS octal  
flip−flip with 3−state output fabricated with silicon gate CMOS  
technology. It achieves high speed operation similar to equivalent  
Bipolar Schottky TTL while maintaining CMOS low power  
dissipation.  
This 8−bit D−type flip−flop is controlled by a clock input and an  
output enable input. When the output enable input is high, the eight  
outputs are in a high impedance state.  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output. The  
inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems  
to 3 V systems.  
http://onsemi.com  
MARKING DIAGRAMS  
20  
SOIC−20  
DW SUFFIX  
CASE 751D  
VHC574  
AWLYYWWG  
20  
1
1
20  
VHC  
574  
TSSOP−20  
DT SUFFIX  
CASE 948E  
• High Speed: f  
= 180 MHz (Typ) at V = 5 V  
CC  
max  
20  
ALYWG  
• Low Power Dissipation: I = 4 μA (Max) at T = 25°C  
CC  
A
1
G
• High Noise Immunity: V  
= V = 28% V  
NIL CC  
NIH  
1
• Power Down Protection Provided on Inputs  
• Balanced Propagation Delays  
VHC574 = Specific Device Code  
A
= Assembly Location  
= Wafer Lot  
• Designed for 2 V to 5.5 V Operating Range  
WL, L  
YY, Y  
WW, W  
G or G  
= Year  
• Low Noise: V  
= 1.2 V (Max)  
OLP  
= Work Week  
= Pb−Free Package  
• Pin and Function Compatible with Other Standard Logic Families  
• Latchup Performance Exceeds 300 mA  
(Note: Microdot may be in either location)  
• ESD Performance: HBM > 2000 V; Machine Model > 200 V  
• Chip Complexity: 266 FETs or 66.5 Equivalent Gates  
• These Devices are Pb−Free and are RoHS Compliant  
ORDERING INFORMATION  
†
Device  
Package  
Shipping  
MC74VHC574DWR2G  
MC74VHC574DWG  
SOIC−20  
1000 / T&R  
38 / Rail  
SOIC−20  
MC74VHC574DTR2G TSSOP−20 2500 / T&R  
MC74VHC574DTG TSSOP−20 75 / Rail  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specification  
Brochure, BRD8011/D.  
© Semiconductor Components Industries, LLC, 2011  
1
Publication Order Number:  
May, 2011 − Rev. 6  
MC74VHC574/D  
12345678

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