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MC74LVX4245_11

更新时间： 2024-11-06 12:22:47
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
10页 138K
描述
Dual Supply Octal Translating Transceiver

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MC74LVX4245_11 数据手册

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MC74LVX4245  
Dual Supply Octal  
Translating Transceiver  
with 3−State Outputs  
The 74LVX4245 is a 24−pin dual−supply, octal translating  
transceiver that is designed to interface between a 5.0 V bus and a 3.0 V  
bus in a mixed 3.0 V / 5.0 V supply environment such as laptop  
computers using a 3.3 V CPU and 5.0 V LCD display. The A port  
interfaces with the 5V bus; the B port interfaces with the 3.0 V bus.  
The Transmit/Receive (T/R) input determines the direction of data  
flow. Transmit (active−High) enables data from the A port to the B  
port. Receive (active−Low) enables data from the B port to the A port.  
The Output Enable (OE) input, when High, disables both A and B  
ports by placing them in 3−State.  
http://onsemi.com  
MARKING  
DIAGRAMS  
24  
24  
SOIC−24  
DW SUFFIX  
CASE 751E  
LVX4245  
AWLYYWWG  
1
1
Features  
• Bi−directional Interface Between 5.0 V and 3.0 V Buses  
• Control Inputs Compatible with TTL Level  
24  
LVX  
4245G  
ALYW  
24  
TSSOP−24  
DT SUFFIX  
CASE 948H  
• 5.0 V Data Flow at A Port and 3.0 V Data Flow at B Port  
• Outputs Source/Sink 24 mA at 5.0 V Bus and 12 mA at 3.0 V Bus  
1
• Guaranteed Simultaneous Switching Noise Level and Dynamic  
1
Threshold Performance  
• Available in SOIC and TSSOP Packages  
• Functionally Compatible with the 74 Series 245  
• These Devices are Pb−Free and are RoHS Compliant  
LVX4245 = Specific Device Code  
A
WL, L  
Y
= Assembly Location  
= Wafer Lot  
= Year  
WW, W  
G or G  
= Work Week  
= Pb−Free Package  
(Note: Microdot may be in either location)  
V
V
OE B0  
B1  
20  
B2  
19  
B3  
18  
B4  
17  
B5  
16  
B6  
15  
B7 GND  
14  
CCB  
CCB  
24  
23  
22  
21  
13  
PIN NAMES  
Pins  
Function  
OE  
T/R  
A0−A7  
Output Enable Input  
Transmit/Receive Input  
Side A 3−State Inputs or 3−State  
Outputs  
1
2
3
4
5
6
7
9
11  
8
10  
12  
B0−B7  
Side B 3−State Inputs or 3−State  
Outputs  
V
T/R A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7 GND GND  
CCA  
Figure 1. 24−Lead Pinout  
(Top View)  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
© Semiconductor Components Industries, LLC, 2011  
1
Publication Order Number:  
May, 2011 − Rev. 5  
MC74LVX4245/D  
1234567...10

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