MC74LVX50
Hex Buffer
The MC74LVX50 is an advanced high speed CMOS buffer
fabricated with silicon gate CMOS technology.
The internal circuit is composed of three stages, including a buffered
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
http://onsemi.com
Features
• High Speed: t = 4.1 ns (Typ) at V = 3.3 V
PD
CC
SOIC−14 NB
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
• Low Power Dissipation: I = 2 mA (Max) at T = 25°C
CC
A
• High Noise Immunity: V
= V = 28% V
NIL CC
NIH
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
PIN ASSIGNMENT
V
A6 Y6 A5 Y5 A4 Y4
• Designed for 2.0 V to 3.6 V Operating Range
CC
14
13
12
11
10
9
8
• Low Noise: V
= 0.5 V (Max)
OLP
• These Devices are Pb−Free and are RoHS Compliant
1
3
5
2
4
6
1
2
3
4
5
6
7
A1
A2
A3
Y1
Y2
A1 Y1 A2 Y2 A3 Y3 GND
14−Lead (Top View)
1
1
1
1
1
1
A1
A2
A3
A4
A5
A6
Y1
Y2
Y3
Y4
Y5
Y6
MARKING DIAGRAMS
Y3
14
Y = A
Y4
LVX50G
9
8
A4
A5
A6
AWLYWW
1
11
13
10
12
Y5
Y6
SOIC−14 NB
14
LVX
50
ALYWG
Figure 1. Logic Diagram
Figure 2. Logic Symbol
G
1
TSSOP−14
FUNCTION TABLE
A Input
LVX50 = Specific Device Code
Y Output
A
= Assembly Location
WL, L = Wafer Lot
= Year
L
L
Y
H
H
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
August, 2014 − Rev. 5
MC74LVX50/D