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MC74LVX540DTR2 PDF预览

MC74LVX540DTR2

更新时间： 2024-01-09 01:44:51
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
8页 100K
描述
IC LV/LV-A/LVX/H SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, TSSOP-20, Bus Driver/Transceiver

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中文翻译

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MC74LVX540DTR2 技术参数

生命周期：Transferred包装说明：TSSOP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.7系列：LV/LV-A/LVX/H
JESD-30 代码：R-PDSO-G20长度：6.5 mm
逻辑集成电路类型：BUS DRIVER位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟（tpd）：17 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：2.7 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL宽度：4.4 mm
Base Number Matches：1

MC74LVX540DTR2 数据手册

 浏览型号MC74LVX540DTR2的Datasheet PDF文件第2页浏览型号MC74LVX540DTR2的Datasheet PDF文件第3页浏览型号MC74LVX540DTR2的Datasheet PDF文件第4页浏览型号MC74LVX540DTR2的Datasheet PDF文件第5页浏览型号MC74LVX540DTR2的Datasheet PDF文件第6页浏览型号MC74LVX540DTR2的Datasheet PDF文件第7页 
MC74LVX540  
Octal Bus Buffer  
Inverting  
The MC74LVX540 is an advanced high speed CMOS inverting  
octal bus buffer fabricated with silicon gate CMOS technology. It  
achieves high speed operation similar to equivalent Bipolar Schottky  
TTL while maintaining CMOS low power dissipation.  
The MC74LVX540 features inputs and outputs on opposite sides of  
the package and two AND−ed active−low output enables. When either  
OE1 or OE2 are high, the terminal outputs are in the high impedance  
state.  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output. The  
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V  
systems to 3.0 V systems.  
http://onsemi.com  
MARKING  
DIAGRAMS  
20  
SOIC−20  
DW SUFFIX  
CASE 751D  
LVX540  
AWLYYWW  
20  
1
1
Features  
20  
• High Speed: t = 5.0 ns (Typ) at V = 3.3 V  
PD  
CC  
• Low Power Dissipation: I = 4 mA (Max) at T = 25°C  
CC  
A
LVX  
540  
ALYW  
TSSOP−20  
DT SUFFIX  
CASE 948E  
• High Noise Immunity: V  
= V = 28% V  
NIL CC  
20  
NIH  
1
• Power Down Protection Provided on Inputs  
• Balanced Propagation Delays  
1
• Designed for 2.0 V to 3.6 V Operating Range  
• Low Noise: V  
= 1.2 V (Max)  
OLP  
20  
• Pin and Function Compatible with Other Standard Logic Families  
• Latchup Performance Exceeds 300 mA  
• Chip Complexity: 124 FETs or 31 Equivalent Gates  
SOEIAJ−20  
M SUFFIX  
CASE 967  
1
74LVX540  
AWLYWW  
20  
1
• ESD Performance:  
Human Body Model > 2000 V;  
Machine Model > 200 V  
A
L, WL  
Y, YY  
= Assembly Location  
= Wafer Lot  
= Year  
• Pb−Free Packages are Available*  
W, WW = Work Week  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 3 of this data sheet.  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
March, 2005 − Rev. 3  
MC74LVX540/D  
12345678

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