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MC74LVX50DR2 PDF预览

MC74LVX50DR2

更新时间: 2024-02-14 15:09:47
品牌 Logo 应用领域
安森美 - ONSEMI 逻辑集成电路光电二极管
页数 文件大小 规格书
10页 146K
描述
HEX BUFFER

MC74LVX50DR2 技术参数

是否无铅: 不含铅生命周期:Active
零件包装代码:SOIC包装说明:SOP, SOP14,.25
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:1.22系列:LV/LV-A/LVX/H
JESD-30 代码:R-PDSO-G14JESD-609代码:e3
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:BUFFER最大I(ol):0.004 A
湿度敏感等级:1功能数量:6
输入次数:1端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:11.5 ns传播延迟(tpd):16 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.75 mm子类别:Gates
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.7 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:3.9 mm
Base Number Matches:1

MC74LVX50DR2 数据手册

 浏览型号MC74LVX50DR2的Datasheet PDF文件第2页浏览型号MC74LVX50DR2的Datasheet PDF文件第3页浏览型号MC74LVX50DR2的Datasheet PDF文件第4页浏览型号MC74LVX50DR2的Datasheet PDF文件第5页浏览型号MC74LVX50DR2的Datasheet PDF文件第6页浏览型号MC74LVX50DR2的Datasheet PDF文件第7页 
MC74LVX50  
Hex Buffer  
The MC74LVX50 is an advanced high speed CMOS buffer  
fabricated with silicon gate CMOS technology.  
The internal circuit is composed of three stages, including a buffered  
output which provides high noise immunity and stable output. The  
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V  
systems to 3.0 V systems.  
http://onsemi.com  
MARKING  
Features  
DIAGRAMS  
High Speed: t = 4.1 ns (Typ) at V = 3.3 V  
PD  
CC  
Low Power Dissipation: I = 2 mA (Max) at T = 25°C  
CC  
A
14  
High Noise Immunity: V  
= V = 28% V  
NIL CC  
NIH  
SOIC−14  
D SUFFIX  
CASE 751A  
LVX50  
AWLYWW  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
Designed for 2.0 V to 3.6 V Operating Range  
14  
1
1
Low Noise: V  
= 0.5 V (Max)  
OLP  
Pb−Free Packages are Available*  
14  
TSSOP−14  
DT SUFFIX  
CASE 948G  
LVX  
50  
ALYW  
14  
1
1
14  
74LVX50  
ALYW  
SOEIAJ−14  
M SUFFIX  
CASE 965  
14  
1
1
A
=
=
=
=
Assembly Location  
Wafer Lot  
Year  
WL or L  
Y
WW or W  
Work Week  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
March, 2005 − Rev. 3  
MC74LVX50/D  

MC74LVX50DR2 替代型号

型号 品牌 替代类型 描述 数据表
MC74LVX50DR2G ONSEMI

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IC LV/LV-A/LVX/H SERIES, HEX 1-INPUT NON-INVERT GATE, PDSO14, EIAJ, SO-14, Gate