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MC74LCX16543ADT PDF预览

MC74LCX16543ADT

更新时间: 2024-11-04 14:53:15
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
8页 75K
描述
LVC/LCX/Z SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, PLASTIC, TSSOP-56

MC74LCX16543ADT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP56,.3,20
针数:56Reach Compliance Code:not_compliant
风险等级:5.56控制类型:INDEPENDENT CONTROL
计数方向:BIDIRECTIONAL系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G56JESD-609代码:e0
长度:14 mm逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.024 A位数:8
功能数量:2端口数量:2
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP56,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
Prop。Delay @ Nom-Sup:5.4 ns传播延迟(tpd):8.2 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:6.1 mm
Base Number Matches:1

MC74LCX16543ADT 数据手册

 浏览型号MC74LCX16543ADT的Datasheet PDF文件第2页浏览型号MC74LCX16543ADT的Datasheet PDF文件第3页浏览型号MC74LCX16543ADT的Datasheet PDF文件第4页浏览型号MC74LCX16543ADT的Datasheet PDF文件第5页浏览型号MC74LCX16543ADT的Datasheet PDF文件第6页浏览型号MC74LCX16543ADT的Datasheet PDF文件第7页 
Low-Voltage CMOS 16-Bit  
MC74LCX16543A  
Latching Transceiver  
With 5V–Tolerant Inputs and Outputs  
(3–State, Non–Inverting)  
The MC74LCX16543A is a high performance, non–inverting  
16–bit latching transceiver operating from a 2.7 to 3.6V supply. The  
device is byte controlled. Each byte has separate control inputs which  
can be tied together for full 16–bit operation. High impedance TTL  
compatible inputs significantly reduce current loading to input drivers  
while TTL compatible outputs offer improved switching noise  
LOW–VOLTAGE CMOS  
16–BIT LATCHING  
TRANSCEIVER  
performance. A V specification of 5.5V allows MC74LCX16543A  
I
inputs to be safely driven from 5V devices. The MC74LCX16543A is  
suitable for memory address driving and all TTL level bus oriented  
transceiver applications.  
For data flow from A to B with the EAB LOW, the A–to–B Output  
Enable (OEAB) must be LOW in order to enable data to the B bus, as  
indicated in the Function Table. With EAB LOW, a LOW signal on the  
A–to–B Latch Enable (LEAB) input makes the A–to–B latches  
transparent; a subsequent LOW–to–HIGH transition of the LEAB  
signal will latch the A latches, and the outputs no longer change with  
the A inputs. With EAB and OEAB both LOW, the 3–State B output  
buffers are active and reflect the data present at the output of the A  
latches. Control of data flow from B to A is symmetric to that above,  
but uses the EBA, LEBA, and OEBA inputs.  
DT SUFFIX  
56–LEAD PLASTIC TSSOP PACKAGE  
CASE 1202–01  
Designed for 2.7 to 3.6V V Operation  
CC  
5.2ns Maximum t  
pd  
5V Tolerant — Interface Capability With 5V TTL Logic  
Supports Live Insertion and Withdrawal  
I  
Specification Guarantees High Impedance When V = 0V  
OFF  
CC  
PIN NAMES  
LVTTL Compatible  
LVCMOS Compatible  
Pins  
Function  
24mA Balanced Output Sink and Source Capability  
OExxn  
Exxn  
LExxn  
A0–A15  
B0–B15  
Output Enable Inputs  
Enable Inputs  
Latch Enable Inputs  
3–State Inputs/Outputs  
3–State Inputs/Outputs  
Near Zero Static Supply Current in All Three Logic States (20µA)  
Substantially Reduces System Power Requirements  
Latchup Performance Exceeds 500mA  
ESD Performance: Human Body Model >2000V; Machine Model >200V  
Semiconductor Components Industries, LLC, 2001  
1
Publication Order Number:  
January, 2001 – Rev. 1  
MC74LCX16543/D  

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