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MC74LCX2245SD PDF预览

MC74LCX2245SD

更新时间： 2024-01-23 22:46:08
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 165K
描述
LOW-VOLTAGE CMOS OCTAL TRANSCEIVER

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中文翻译

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MC74LCX2245SD 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SSOP包装说明：SSOP,
针数：20Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.31
Is Samacsys：N其他特性：WITH DIRECTION CONTROL
系列：LVC/LCX/ZJESD-30 代码：R-PDSO-G20
JESD-609代码：e0长度：7.2 mm
逻辑集成电路类型：BUS TRANSCEIVER位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
传播延迟（tpd）：11 ns认证状态：Not Qualified
座面最大高度：1.99 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：5.29 mmBase Number Matches：1

MC74LCX2245SD 数据手册

 浏览型号MC74LCX2245SD的Datasheet PDF文件第2页浏览型号MC74LCX2245SD的Datasheet PDF文件第3页浏览型号MC74LCX2245SD的Datasheet PDF文件第4页浏览型号MC74LCX2245SD的Datasheet PDF文件第5页浏览型号MC74LCX2245SD的Datasheet PDF文件第6页浏览型号MC74LCX2245SD的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
The MC74LCX2245 is a high performance, non–inverting octal  
transceiver operating from a 2.7 to 3.6V supply. High impedance TTL  
compatible inputs significantly reduce current loading to input drivers  
while TTL compatible outputs offer improved switching noise  
LOW–VOLTAGE CMOS  
OCTAL TRANSCEIVER  
performance. A V specification of 5.5V allows MC74LCX2245 inputs to  
I
be safely driven from 5V devices. The MC74LCX2245 is designed to  
reduce output overshoot and undershoot and is suitable for memory  
address driving and all TTL level bus oriented transceiver applications;  
especially those requiring the very quiet outputs.  
Current drive capability is 12mA at both A and B ports. The  
Transmit/Receive (T/R) input determines the direction of data flow  
through the bi–directional transceiver. Transmit (active–HIGH) enables  
data from A ports to B ports; Receive (active–LOW) enables data from B  
to A ports. The Output Enable input, when HIGH, disables both A and B  
ports by placing them in a HIGH Z condition.  
DW SUFFIX  
20–LEAD PLASTIC SOIC  
CASE 751D–04  
M SUFFIX  
20–LEAD PLASTIC SOIC EIAJ  
CASE 967–01  
• Designed for 2.7 to 3.6V V  
CC  
• 5V Tolerant — Interface Capability With 5V TTL Logic  
• Supports Live Insertion and Withdrawal  
Operation  
• I  
OFF  
Specification Guarantees High Impedance When V  
= 0V  
CC  
• LVTTL Compatible  
SD SUFFIX  
20–LEADPLASTIC SSOP  
CASE 940C–03  
• LVCMOS Compatible  
• 12mA Balanced Output Sink and Source Capability  
• Near Zero Static Supply Current in All Three Logic States (10µA)  
Substantially Reduces System Power Requirements  
• Latchup Performance Exceeds 500mA  
DT SUFFIX  
20–LEAD PLASTIC TSSOP  
CASE 948E–02  
• ESD Performance: Human Body Model >2000V; Machine Model >200V  
V
OE  
19  
B0  
18  
B1  
17  
B2  
16  
B3  
15  
B4  
14  
B5  
13  
B6  
12  
B7  
11  
CC  
20  
PIN NAMES  
Pins  
Function  
OE  
T/R  
A0–A7  
Output Enable Input  
Transmit/Receive Input  
Side A 3–State Inputs or 3–State  
Outputs  
1
2
3
4
5
6
7
9
8
10  
T/R  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
GND  
B0–B7  
Side B 3–State Inputs or 3–State  
Outputs  
Figure 1. 20–Lead Pinout  
(Top View)  
This document contains information on a product under development. Motorola reserves the right to change or  
discontinue this product without notice.  
1/97  
REV 0  
Motorola, Inc. 1997  
12345678

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