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MC74LCX16543DTR2 PDF预览

MC74LCX16543DTR2

更新时间： 2024-11-04 14:53:15
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
19页 526K
描述
LVC/LCX/Z SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, PLASTIC, TSSOP-56

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中文翻译

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MC74LCX16543DTR2 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP,
针数：56Reach Compliance Code：compliant
风险等级：5.56系列：LVC/LCX/Z
JESD-30 代码：R-PDSO-G56JESD-609代码：e0
长度：14 mm逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
位数：8功能数量：2
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：225传播延迟（tpd）：7.5 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：6.1 mm
Base Number Matches：1

MC74LCX16543DTR2 数据手册

 浏览型号MC74LCX16543DTR2的Datasheet PDF文件第2页浏览型号MC74LCX16543DTR2的Datasheet PDF文件第3页浏览型号MC74LCX16543DTR2的Datasheet PDF文件第4页浏览型号MC74LCX16543DTR2的Datasheet PDF文件第5页浏览型号MC74LCX16543DTR2的Datasheet PDF文件第6页浏览型号MC74LCX16543DTR2的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
The MC74LCX16543 is a high performance, non–inverting 16–bit  
latching transceiver operating from a 2.7 to 3.6V supply. The device is  
byte controlled. Each byte has separate control inputs which can be tied  
together for full 16–bit operation. High impedance TTL compatible inputs  
significantly reduce current loading to input drivers while TTL compatible  
LOW–VOLTAGE CMOS  
16–BIT LATCHING  
TRANSCEIVER  
outputs offer improved switching noise performance. A V specification of  
I
5.5V allows MC74LCX16543 inputs to be safely driven from 5V devices.  
The MC74LCX16543 is suitable for memory address driving and all TTL  
level bus oriented transceiver applications.  
For data flow from A to B with the EAB LOW, the A–to–B Output  
Enable (OEAB) must be LOW in order to enable data to the B bus, as  
indicated in the Function Table. With EAB LOW, a LOW signal on the  
A–to–B Latch Enable (LEAB) input makes the A–to–B latches  
transparent; a subsequent LOW–to–HIGH transition of the LEAB signal  
will latch the A latches, and the outputs no longer change with the A  
inputs. With EAB and OEAB both LOW, the 3–State B output buffers are  
active and reflect the data present at the output of the A latches. Control  
of data flow from B to A is symetric to that above, but uses the EBA,  
LEBA, and OEBA inputs.  
DT SUFFIX  
PLASTIC TSSOP PACKAGE  
CASE 1202–01  
• Designed for 2.7 to 3.6V V  
CC  
Operation  
• 5.2ns Maximum t  
pd  
• 5V Tolerant — Interface Capability With 5V TTL Logic  
• Supports Live Insertion and Withdrawal  
• I  
OFF  
Specification Guarantees High Impedance When V  
= 0V  
CC  
PIN NAMES  
• LVTTL Compatible  
• LVCMOS Compatible  
Pins  
Function  
• 24mA Balanced Output Sink and Source Capability  
OExxn  
Exxn  
LExxn  
A0–A15  
B0–B15  
Output Enable Inputs  
Enable Inputs  
Latch Enable Inputs  
3–State Inputs/Outputs  
3–State Inputs/Outputs  
• Near Zero Static Supply Current in All Three Logic States (20µA)  
Substantially Reduces System Power Requirements  
• Latchup Performance Exceeds 500mA  
• ESD Performance: Human Body Model >2000V; Machine Model >200V  
This document contains information on a new product. Specifications and information herein are subject to  
change without notice.  
11/96  
REV 0.2  
199  
Motorola, Inc. 1996  
1234567...19

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MC74LCX16646DTR2 MOTOROLA

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MC74LCX16652DTR2 MOTOROLA

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 		LVC/LCX/Z SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, PLASTIC, TSSOP-5
MC74LCX16652DTR2 ONSEMI

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 		LVC/LCX/Z SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, PLASTIC, TSSOP-5
MC74LCX2245 MOTOROLA

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