Datasheet > MC74HCT273A_14

MC74HCT273A_14

更新时间： 2024-11-07 01:17:27

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
6页	118K
描述
Octal D Flip-Flop with Common Clock and Reset with LSTTL-Compatible Inputs

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MC74HCT273A_14 数据手册

MC74HCT273A

Octal D Flip-Flop with

Common Clock and Reset

with LSTTL-Compatible

Inputs

http://onsemi.com

High−Performance Silicon−Gate CMOS

The MC74HCT273A may be used as a level converter for

interfacing TTL or NMOS outputs to High−Speed CMOS inputs.

The HCT273A is identical in pinout to the LS273.

This device consists of eight D flip−flops with common Clock and

Reset inputs. Each flip−flop is loaded with a low−to−high transition of

the Clock input. Reset is asynchronous and active low.

SOIC−20W

DW SUFFIX

CASE 751D

TSSOP−20

DT SUFFIX

CASE 948E

PIN ASSIGNMENT

Features

RESET

• Output Drive Capability: 10 LSTTL Loads

• TTL/NMOS Compatible Input Levels

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 4.5 V to 5.5 V

• Low Input Current: 1.0 mA

CLOCK

GND

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7 A

• Chip Complexity: 284 FETs or 71 Equivalent Gates

• These Devices are Pb−Free and are RoHS Compliant

MARKING DIAGRAMS

HCT

HCT273A

AWLYYWWG

273A

ALYWG

SOIC−20W

TSSOP−20

DATA

INPUTS

= Assembly Location

= Wafer Lot

= Year

NONINVERTING

OUTPUTS

WL, L

YY, Y

WW, W = Work Week

G or G

= Pb−Free Package

(Note: Microdot may be in either location)

FUNCTION TABLE

CLOCK

Inputs

Output

Reset Clock

PIN 20 = V

PIN 10 = GND

RESET

Figure 1. Logic Diagram

No Change

X = Don’t Care

Z = High Impedance

ORDERING INFORMATION

See detailed ordering and shipping information on page 4 of

this data sheet.

Publication Order Number:

September, 2014 − Rev. 12

MC74HCT273A/D

12 3 4 5 6

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