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MC74HCT273ADTR2 PDF预览

MC74HCT273ADTR2

更新时间: 2024-11-21 14:53:15
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
6页 111K
描述
IC,FLIP-FLOP,OCTAL,D TYPE,HCT-CMOS,TSSOP,20PIN,PLASTIC, DIP-20

MC74HCT273ADTR2 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete包装说明:DIP-20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.67Is Samacsys:N
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:20000000 Hz最大I(ol):0.004 A
湿度敏感等级:1功能数量:8
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL电源:5 V
认证状态:Not Qualified子类别:FF/Latches
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
触发器类型:POSITIVE EDGEBase Number Matches:1

MC74HCT273ADTR2 数据手册

 浏览型号MC74HCT273ADTR2的Datasheet PDF文件第2页浏览型号MC74HCT273ADTR2的Datasheet PDF文件第3页浏览型号MC74HCT273ADTR2的Datasheet PDF文件第4页浏览型号MC74HCT273ADTR2的Datasheet PDF文件第5页浏览型号MC74HCT273ADTR2的Datasheet PDF文件第6页 
MC74HCT273A  
Octal D Flip-Flop with  
Common Clock and Reset  
with LSTTL-Compatible  
Inputs  
http://onsemi.com  
High−Performance Silicon−Gate CMOS  
The MC74HCT273A may be used as a level converter for  
interfacing TTL or NMOS outputs to High−Speed CMOS inputs.  
The HCT273A is identical in pinout to the LS273.  
This device consists of eight D flip−flops with common Clock and  
Reset inputs. Each flip−flop is loaded with a low−to−high transition of  
the Clock input. Reset is asynchronous and active low.  
SOIC−20W  
DW SUFFIX  
CASE 751D  
TSSOP−20  
DT SUFFIX  
CASE 948E  
PIN ASSIGNMENT  
Features  
V
RESET  
Q0  
D0  
1
2
3
CC  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
Q7  
D7  
Output Drive Capability: 10 LSTTL Loads  
TTL/NMOS Compatible Input Levels  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 4.5 V to 5.5 V  
Low Input Current: 1.0 mA  
D6  
D1  
4
5
6
7
8
9
Q6  
Q5  
Q1  
Q2  
D5  
D2  
D4  
D3  
Q4  
CLOCK  
Q3  
GND  
In Compliance with the Requirements Defined by JEDEC Standard  
10  
No. 7 A  
Chip Complexity: 284 FETs or 71 Equivalent Gates  
These Devices are Pb−Free and are RoHS Compliant  
MARKING DIAGRAMS  
20  
20  
1
HCT  
HCT273A  
AWLYYWWG  
273A  
ALYWG  
G
2
3
Q0  
D0  
5
6
4
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
1
7
SOIC−20W  
TSSOP−20  
8
9
DATA  
INPUTS  
A
= Assembly Location  
= Wafer Lot  
= Year  
NONINVERTING  
OUTPUTS  
13  
14  
17  
18  
WL, L  
YY, Y  
12  
15  
16  
19  
WW, W = Work Week  
G or G  
= Pb−Free Package  
(Note: Microdot may be in either location)  
11  
FUNCTION TABLE  
CLOCK  
Inputs  
Output  
Q
Reset Clock  
D
PIN 20 = V  
CC  
PIN 10 = GND  
L
X
L
X
H
L
X
X
L
H
L
1
RESET  
H
H
H
H
Figure 1. Logic Diagram  
No Change  
No Change  
X = Don’t Care  
Z = High Impedance  
ORDERING INFORMATION  
See detailed ordering and shipping information on page 4 of  
this data sheet.  
© Semiconductor Components Industries, LLC, 2014  
1
Publication Order Number:  
September, 2014 − Rev. 12  
MC74HCT273A/D  

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