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MC74HCT273AN

更新时间: 2024-11-05 23:01:35
品牌 Logo 应用领域
安森美 - ONSEMI 触发器逻辑集成电路光电二极管时钟
页数 文件大小 规格书
8页 155K
描述
Octal D Flip-Flop with Common Clock and Reset with LSTTL-Compatible Inputs

MC74HCT273AN 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP20,.3
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.23系列:HCT
JESD-30 代码:R-PDIP-T20JESD-609代码:e0
长度:26.415 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:20000000 Hz
最大I(ol):0.004 A位数:8
功能数量:1端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
包装方法:RAIL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V传播延迟(tpd):35 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:20 MHz

MC74HCT273AN 数据手册

 浏览型号MC74HCT273AN的Datasheet PDF文件第2页浏览型号MC74HCT273AN的Datasheet PDF文件第3页浏览型号MC74HCT273AN的Datasheet PDF文件第4页浏览型号MC74HCT273AN的Datasheet PDF文件第5页浏览型号MC74HCT273AN的Datasheet PDF文件第6页浏览型号MC74HCT273AN的Datasheet PDF文件第7页 
http://onsemi.com  
High–Performance Silicon–Gate CMOS  
MARKING  
DIAGRAMS  
20  
The MC74HCT273A may be used as a level converter for  
interfacing TTL or NMOS outputs to High–Speed CMOS inputs.  
The HCT273A is identical in pinout to the LS273.  
This device consists of eight D flip–flops with common Clock and  
Reset inputs. Each flip–flop is loaded with a low–to–high transition of  
the Clock input. Reset is asynchronous and active low.  
PDIP–20  
N SUFFIX  
CASE 738  
MC74HCT273AN  
AWLYYWW  
20  
1
1
20  
Output Drive Capability: 10 LSTTL Loads  
TTL/NMOS Compatible Input Levels  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 4.5 to 5.5 V  
Low Input Current: 1.0 µA  
SOIC WIDE–20  
DW SUFFIX  
CASE 751D  
HCT273A  
AWLYYWW  
20  
1
1
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
Chip Complexity: 284 FETs or 71 Equivalent Gates  
PIN ASSIGNMENT  
LOGIC DIAGRAM  
2
RESET  
Q0  
1
2
3
4
5
6
7
8
9
20  
V
CC  
3
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
5
6
19 Q7  
18 D7  
17 D6  
16 Q6  
15 Q5  
14 D5  
13 D4  
12 Q4  
11 CLOCK  
4
D0  
7
D1  
8
9
DATA  
INPUTS  
NONINVERTING  
OUTPUTS  
13  
14  
17  
18  
Q1  
12  
15  
16  
19  
Q2  
D2  
D3  
Q3  
11  
CLOCK  
GND 10  
PIN 20 = V  
CC  
PIN 10 = GND  
1
RESET  
FUNCTION TABLE  
ORDERING INFORMATION  
Inputs  
Reset Clock  
Output  
Device  
Package  
PDIP–20  
Shipping  
D
Q
MC74HCT273AN  
1440 / Box  
38 / Rail  
L
X
X
H
L
X
X
L
H
L
MC74HCT273ADW  
SOIC–WIDE  
H
H
H
H
MC74HCT273ADWR2 SOIC–WIDE 1000 / Reel  
L
No Change  
No Change  
X = Don’t Care  
Z = High Impedance  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 8  
MC74HCT273A/D  

MC74HCT273AN 替代型号

型号 品牌 替代类型 描述 数据表
SN74HCT273DWR TI

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OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
CD74HCT273E TI

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High Speed CMOS Logic Octal D-Type Flip-Flop with Reset
SN74HCT273N TI

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OCTAL D-TYPE FLIP-FLOPS WITH CLEAR

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