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MC74HCT273A_11

更新时间: 2024-11-24 11:58:47
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安森美 - ONSEMI 触发器时钟
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7页 141K
描述
Octal D Flip-Flop with Common Clock and Reset with LSTTL-Compatible Inputs

MC74HCT273A_11 数据手册

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MC74HCT273A  
Octal D Flip-Flop with  
Common Clock and Reset  
with LSTTL-Compatible  
Inputs  
http://onsemi.com  
HighPerformance SiliconGate CMOS  
The MC74HCT273A may be used as a level converter for  
interfacing TTL or NMOS outputs to HighSpeed CMOS inputs.  
The HCT273A is identical in pinout to the LS273.  
PDIP20  
N SUFFIX  
CASE 738  
This device consists of eight D flipflops with common Clock and  
Reset inputs. Each flipflop is loaded with a lowtohigh transition of  
the Clock input. Reset is asynchronous and active low.  
1
SOIC20W  
DW SUFFIX  
CASE 751D  
Features  
1
Output Drive Capability: 10 LSTTL Loads  
TTL/NMOS Compatible Input Levels  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 4.5 V to 5.5 V  
Low Input Current: 1.0 μA  
TSSOP20  
DT SUFFIX  
CASE 948E  
1
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7 A  
PIN ASSIGNMENT  
Chip Complexity: 284 FETs or 71 Equivalent Gates  
RESET  
Q0  
1
2
3
4
5
6
7
8
9
20  
V
CC  
These Devices are PbFree and are RoHS Compliant  
19 Q7  
18 D7  
17 D6  
16 Q6  
15 Q5  
14 D5  
13 D4  
12 Q4  
11 CLOCK  
D0  
D1  
Q1  
2
3
Q0  
D0  
Q2  
5
6
4
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D2  
7
D3  
8
9
DATA  
Q3  
NONINVERTING  
OUTPUTS  
13  
14  
17  
18  
INPUTS  
12  
15  
16  
19  
GND 10  
FUNCTION TABLE  
Inputs  
Output  
Reset Clock  
D
Q
11  
CLOCK  
L
X
X
H
L
X
X
L
H
L
H
H
H
H
PIN 20 = V  
CC  
PIN 10 = GND  
1
L
No Change  
No Change  
RESET  
X = Don’t Care  
Z = High Impedance  
Figure 1. Logic Diagram  
ORDERING INFORMATION  
See detailed ordering, shipping information, and marking  
information in the package dimensions section on page 5 of  
this data sheet.  
© Semiconductor Components Industries, LLC, 2011  
1
Publication Order Number:  
May, 2011 Rev. 11  
MC74HCT273A/D  

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