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MC74AC273DT PDF预览

MC74AC273DT

更新时间: 2024-11-05 21:53:43
品牌 Logo 应用领域
安森美 - ONSEMI 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
12页 109K
描述
OCTAL D FLIP-FLOP

MC74AC273DT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP20,.25
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.13
系列:ACJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:6.5 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:75000000 Hz最大I(ol):0.012 A
湿度敏感等级:1位数:8
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3/5 V
传播延迟(tpd):14.5 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:4.4 mm最小 fmax:125 MHz
Base Number Matches:1

MC74AC273DT 数据手册

 浏览型号MC74AC273DT的Datasheet PDF文件第2页浏览型号MC74AC273DT的Datasheet PDF文件第3页浏览型号MC74AC273DT的Datasheet PDF文件第4页浏览型号MC74AC273DT的Datasheet PDF文件第5页浏览型号MC74AC273DT的Datasheet PDF文件第6页浏览型号MC74AC273DT的Datasheet PDF文件第7页 
MC74AC273, MC74ACT273  
Octal D Flip-Flop  
The MC74AC273/74ACT273 has eight edge-triggered D–type  
flip–flops with individual D inputs and Q outputs. The common  
buffered Clock (CP) and Master Reset (MR) inputs load and reset  
(clear) all flip–flops simultaneously.  
The register is fully edge-triggered. The state of each D input, one  
setup time before the LOW–to–HIGH clock transition, is transferred  
to the corresponding flip–flop’s Q output.  
All outputs will be forced LOW independently of Clock or Data  
inputs by a LOW voltage level on the MR input. The device is useful  
for applications where the true output only is required and the Clock  
and Master Reset are common to all storage elements.  
http://onsemi.com  
PDIP–20  
N SUFFIX  
CASE 738  
20  
1
SO–20  
Ideal Buffer for MOS Microprocessor or Memory  
Eight Edge-Triggered D Flip–Flops  
Buffered Common Clock  
Buffered, Asynchronous Master Reset  
See MC74AC377 for Clock Enable Version  
See MC74AC373 for Transparent Latch Version  
See MC74AC374 for 3-State Version  
Outputs Source/Sink 24 mA  
DW SUFFIX  
CASE 751  
20  
1
TSSOP–20  
DT SUFFIX  
CASE 948E  
20  
1
EIAJ–20  
M SUFFIX  
CASE 967  
20  
ACT273 Has TTL Compatible Inputs  
1
V
Q
D
D
Q
Q
D
D
Q
4
CP  
11  
CC  
7
7
6
6
5
5
4
ORDERING INFORMATION  
20  
19  
18  
17  
16  
15  
14  
12  
13  
Device  
Package  
PDIP–20  
PDIP–20  
SOIC–20  
Shipping  
MC74AC273N  
18 Units/Rail  
18 Units/Rail  
38 Units/Rail  
MC74ACT273N  
MC74AC273DW  
MC74AC273DWR2  
MC74ACT273DW  
1
2
3
4
5
6
7
9
SOIC–20 1000 Tape & Reel  
SOIC–20 38 Units/Rail  
8
10  
MR  
Q
0
D
0
D
1
Q
1
Q
2
D
2
D
3
Q
3
GND  
Figure 1. Pinout: 20–Lead Packages Conductors  
MC74ACT273DWR2 SOIC–20 1000 Tape & Reel  
(Top View)  
MC74AC273DT  
MC74AC273DTR2  
MC74ACT273DT  
TSSOP–20  
TSSOP–20 2500 Tape & Reel  
TSSOP–20 75 Units/Rail  
75 Units/Rail  
PIN ASSIGNMENT  
PIN  
D0–D  
MR  
FUNCTION  
MC74ACT273DTR2 TSSOP–20 2500 Tape & Reel  
Data Inputs  
7
MC74AC273M  
EIAJ–20  
EIAJ–20 2000 Tape & Reel  
EIAJ–20 40 Units/Rail  
EIAJ–20 2000 Tape & Reel  
40 Units/Rail  
Master Reset  
Clock Pulse Input  
Data Outputs  
CP  
MC74AC273MEL  
MC74ACT273M  
MC74ACT273MEL  
Q –Q  
0
7
DEVICE MARKING INFORMATION  
See general marking information in the device marking  
section on page 7 of this data sheet.  
Semiconductor Components Industries, LLC, 2001  
1
Publication Order Number:  
May, 2001 – Rev. 5  
MC74AC273/D  

MC74AC273DT 替代型号

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