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MC74AC273DW PDF预览

MC74AC273DW

更新时间: 2024-11-22 22:46:23
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器
页数 文件大小 规格书
7页 191K
描述
OCTAL D FLIP-FLOP

MC74AC273DW 数据手册

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OCTAL D FLIP-FLOP  
The MC74AC273/74ACT273 has eight edge-triggered D-type flip-flops with  
individual D inputs and Q outputs. The common buffered Clock (CP) and Master  
Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.  
The register is fully edge-triggered. The state of each D input, one setup time  
before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-  
flop’s Q output.  
All outputs will be forced LOW independently of Clock or Data inputs by a LOW  
voltage level on the MR input. The device is useful for applications where the true  
output only is required and the Clock and Master Reset are common to all storage  
elements.  
Ideal Buffer for MOS Microprocessor or Memory  
Eight Edge-Triggered D Flip-Flops  
Buffered Common Clock  
Buffered, Asynchronous Master Reset  
See MC74AC377 for Clock Enable Version  
See MC74AC373 for Transparent Latch Version  
See MC74AC374 for 3-State Version  
Outputs Source/Sink 24 mA  
N SUFFIX  
CASE 738-03  
PLASTIC  
• ′ACT273 Has TTL Compatible Inputs  
DW SUFFIX  
CASE 751D-04  
PLASTIC  
V
Q
D
D
Q
Q
D
D
Q
4
CP  
11  
CC  
7
7
6
6
5
5
4
20  
19  
18  
17  
16  
15  
14  
12  
13  
LOGIC SYMBOL  
1
2
3
4
5
6
7
9
8
10  
D
CP  
D
Q
D
Q
D
Q
D
Q
D
D
Q
D
Q
0
1
2
3
4
5
6
7
MR  
Q
D
D
Q
Q
D
D
Q
3
GND  
0
0
1
1
2
2
3
MR  
Q
Q
5
0
1
2
3
4
6
7
PIN NAMES  
D –D  
0
Data Inputs  
Master Reset  
7
MR  
CP  
Q –Q  
0
Clock Pulse Input  
Data Outputs  
7
FACT DATA  
5-1  

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