Datasheet > MC54HCT373AJ

MC54HCT373AJ

更新时间： 2024-10-15 00:01:07

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		锁存器
页数	文件大小	规格书
9页	125K
描述
Octal 3-State Noninverting Transparent Latch with LSTTL-Compatible Inputs

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MC54HCT373AJ 数据手册

SEMICONDUCTOR TECHNICAL DATA

J SUFFIX

CERAMIC PACKAGE

CASE 732–03

High–Performance Silicon–Gate CMOS

The MC54/74HCT373A may be used as a level converter for

interfacing TTL or NMOS outputs to High–Speed CMOS inputs.

The HCT373A is identical in pinout to the LS373.

The eight latches of the HCT373A are transparent D–type latches.

While the Latch Enable is high the Q outputs follow the Data Inputs. When

Latch Enable is taken low, data meeting the setup and hold times

becomes latched.

The Output Enable does not affect the state of the latch, but when

Output Enable is high, all outputs are forced to the high–impedance state.

Thus, data may be latched even when the outputs are not enabled.

The HCT373A is identical in function to the HCT573A, which has the

input pins on the opposite side of the package from the output pins. This

device is similar in function to the HCT533A, which has inverting outputs.

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

DW SUFFIX

SOIC PACKAGE

CASE 751D–04

SD SUFFIX

SSOP PACKAGE

CASE 940C–03

DT SUFFIX

TSSOP PACKAGE

CASE 948E–02

•

Output Drive Capability: 15 LSTTL Loads

TTL/NMOS–Compatible Input Levels

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 4.5 to 5.5 V

Low Input Current: 1.0 µA

ORDERING INFORMATION

MC54HCTXXXAJ

MC74HCTXXXAN

MC74HCTXXXADW

MC74HCTXXXASD

MC74HCTXXXADT

Ceramic

Plastic

SOIC

SSOP

TSSOP

In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

•

Chip Complexity: 196 FETs or 49 Equivalent Gates

LOGIC DIAGRAM

PIN ASSIGNMENT

OUTPUT

ENABLE

DATA

INPUTS

NONINVERTING

OUTPUTS

LATCH

ENABLE

GND

PIN 20 = V

PIN 10 = GND

LATCH ENABLE

OUTPUT ENABLE

FUNCTION TABLE

Inputs

Output

Design Criteria

Internal Gate Count*

Value

Units

ea.

Output Latch

Enable Enable

Internal Gate Propagation Delay

Internal Gate Power Dissipation

1.5

No Change

5.0

µW

X = don’t care

Z = high impedance

Speed Power Product

.0075

* Equivalent to a two–input NAND gate.

2/97

REV 7

Motorola, Inc. 1997

12 3 4 5 6 7...9

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与MC54HCT373AJ相关器件

型号	品牌	获取价格	描述	数据表
MC54HCT374A	MOTOROLA	获取价格	OCTAL 3-STATE NONINVERTING D FLIP-FLOP WITH LSTTL-COM
MC54HCT374AJ	MOTOROLA	获取价格	Octal 3-State Noninverting D Flip-Flop with LSTTL-Compatible Inputs
MC54HCT533AJD	ROCHESTER	获取价格	Bus Driver
MC54HCT533JDS	ROCHESTER	获取价格	Bus Driver
MC54HCT533JS	ROCHESTER	获取价格	Bus Driver
MC54HCT534AJ	MOTOROLA	获取价格	IC,FLIP-FLOP,OCTAL,D TYPE,HCT-CMOS,DIP,20PIN,CERAMIC
MC54HCT534JS	MOTOROLA	获取价格	D Flip-Flop, 8-Func, Positive Edge Triggered, CMOS, CDIP20
MC54HCT540J	MOTOROLA	获取价格	HCT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, CDIP20, CERAMIC, DIP-20
MC54HCT541JD	MOTOROLA	获取价格	Bus Driver, HCT Series, 1-Func, 8-Bit, True Output, CMOS, CDIP20, CERAMIC, DIP-20
MC54HCT573AJ	MOTOROLA	获取价格	HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20, CERAMIC, DIP-20

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