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MC54HCT374AJ PDF预览

MC54HCT374AJ

更新时间: 2024-11-15 00:01:07
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 总线驱动器总线收发器触发器逻辑集成电路
页数 文件大小 规格书
8页 124K
描述
Octal 3-State Noninverting D Flip-Flop with LSTTL-Compatible Inputs

MC54HCT374AJ 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP,
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.15
系列:HCTJESD-30 代码:R-CDIP-T20
JESD-609代码:e0长度:24.515 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):47 ns
认证状态:Not Qualified座面最大高度:5.08 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

MC54HCT374AJ 数据手册

 浏览型号MC54HCT374AJ的Datasheet PDF文件第2页浏览型号MC54HCT374AJ的Datasheet PDF文件第3页浏览型号MC54HCT374AJ的Datasheet PDF文件第4页浏览型号MC54HCT374AJ的Datasheet PDF文件第5页浏览型号MC54HCT374AJ的Datasheet PDF文件第6页浏览型号MC54HCT374AJ的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
J SUFFIX  
CERAMIC PACKAGE  
CASE 732–03  
20  
20  
High–Performance Silicon–Gate CMOS  
1
The MC54/74HCT374A may be used as a level converter for  
interfacing TTL or NMOS outputs to High–Speed CMOS inputs.  
The HCT374A is identical in pinout to the LS374.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 738–03  
Data meeting the setup and hold time is clocked to the outputs with the  
rising edge of Clock. The Output Enable does not affect the state of the  
flip–flops, but when Output Enable is high, the outputs are forced to the  
high–impedance state. Thus, data may be stored even when the outputs  
are not enabled.  
The HCT374A is identical in function to the HCT574A, which has the  
input pins on the opposite side of the package from the output pins. This  
device is similar in function to the HCT534A, which has inverting outputs.  
1
DW SUFFIX  
SOIC PACKAGE  
CASE 751D–04  
20  
20  
20  
1
SD SUFFIX  
SSOP PACKAGE  
CASE 940C–03  
1
DT SUFFIX  
TSSOP PACKAGE  
CASE 948E–02  
Output Drive Capability: 15 LSTTL Loads  
TTL/NMOS–Compatible Input Levels  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 4.5 to 5.5 V  
Low Input Current: 1.0 µA  
1
ORDERING INFORMATION  
MC54HCTXXXAJ  
MC74HCTXXXAN  
MC74HCTXXXADW  
MC74HCTXXXASD  
MC74HCTXXXADT  
Ceramic  
Plastic  
SOIC  
SSOP  
TSSOP  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
Chip Complexity: 276 FETs or 69 Equivalent Gates  
Improvements over HCT374  
— Improved Propagation Delays  
— 50% Lower Quiescent Power  
— Improved Input Noise and Latchup Immunity  
PIN ASSIGNMENT  
OUTPUT  
ENABLE  
1
20  
V
CC  
LOGIC DIAGRAM  
Q0  
D0  
D1  
2
3
4
19  
18  
17  
Q7  
D7  
D6  
2
5
3
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
D0  
D1  
D2  
D3  
D4  
4
Q1  
Q2  
5
16  
15  
14  
13  
12  
11  
Q6  
6
7
6
Q5  
9
8
DATA  
INPUTS  
NONINVERTING  
OUTPUTS  
D2  
7
D5  
13  
14  
17  
18  
12  
15  
16  
D3  
8
D4  
D5  
D6  
D7  
Q3  
9
Q4  
GND  
10  
CLOCK  
19  
Q7  
11  
CLOCK  
FUNCTION TABLE  
PIN 20 = V  
PIN 10 = GND  
CC  
Inputs  
Output  
1
OUTPUT ENABLE  
Output  
Enable Clock  
D
Q
Design Criteria  
Internal Gate Count*  
Value  
Units  
L
L
H
L
X
X
H
69  
1.5  
ea.  
L
No Change  
Z
L
H
L,H,  
X
Internal Gate Propagation Delay  
Internal Gate Power Dissipation  
ns  
µW  
pJ  
5.0  
X = don’t care  
Z = high impedance  
Speed Power Product  
.0075  
* Equivalent to a two–input NAND gate.  
2/97  
REV 7  
Motorola, Inc. 1997  

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