Datasheet > MC54HCT74AJ

MC54HCT74AJ

更新时间： 2024-11-15 11:08:55

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		触发器逻辑集成电路
页数	文件大小	规格书
5页	190K
描述
Dual D Flip-Flop with Set and Reset with LSTTL Compatible Inputs

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MC54HCT74AJ 数据手册

SEMICONDUCTOR TECHNICAL DATA

N SUFFIX

PLASTIC PACKAGE

CASE 646–06

High–Performance Silicon–Gate CMOS

The MC74HCT74A is identical in pinout to the LS74. This device may be

used as a level converter for interfacing TTL or NMOS outputs to High Speed

CMOS inputs.

This device consists of two D flip–flops with individual Set, Reset, and

Clock inputs. Information at a D–input is transferred to the corresponding Q

output on the next positive going edge of the clock input. Both Q and Q

outputs are available from each flip–flop. The Set and Reset inputs are

asynchronous.

D SUFFIX

SOIC PACKAGE

CASE 751A–03

ORDERING INFORMATION

MC54HCTXXAJ

MC74HCTXXAN

MC74HCTXXAD

Ceramic

Plastic

SOIC

•

Output Drive Capability: 10 LSTTL Loads

TTL NMOS Compatible Input Levels

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 4.5 to 5.5 V

Low Input Current: 1.0 µA

PIN ASSIGNMENT

In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

RESET 1

DATA 1

•

Chip Complexity: 136 FETs or 34 Equivalent Gates

RESET 2

LOGIC DIAGRAM

CLOCK 1

SET 1

DATA 2

CLOCK 2

RESET 1

SET 2

DATA 1

GND

CLOCK 1

SET 1

FUNCTION TABLE

RESET 2

Inputs

Set Reset Clock Data

Outputs

DATA 2

CLOCK 2

SET 2

No Change

PIN 14 = V

PIN 7 = GND

* Both outputs will remain high as long as

Set and Reset are low, but the output

states are unpredictable if Set and Reset

go high simultaneously.

Design Criteria

Internal Gate Count*

Value

Units

ea.

Internal Gate Propagation Delay

Internal Gate Power Dissipation

Speed Power Product

1.5

5.0

µW

.0075

* Equivalent to a two–input NAND gate.

10/95

REV 6

Motorola, Inc. 1995

12 3 4 5

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