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MC54HCT574AJ PDF预览

MC54HCT574AJ

更新时间: 2024-11-15 00:01:07
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器
页数 文件大小 规格书
7页 100K
描述
Octal 3-State Noninverting D Flip-Flop with LSTTL-Compatible Inputs

MC54HCT574AJ 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP,Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.92
其他特性:BROADSIDE VERSION OF 374系列:HCT
JESD-30 代码:R-CDIP-T20JESD-609代码:e0
长度:24.515 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):45 ns认证状态:Not Qualified
座面最大高度:5.08 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

MC54HCT574AJ 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
J SUFFIX  
CERAMIC PACKAGE  
CASE 732–03  
High–Performance Silicon–Gate CMOS  
20  
20  
1
The MC54/74HCT574A is identical in pinout to the LS574. This device  
may be used as a level converter for interfacing TTL or NMOS outputs to  
High Speed CMOS inputs.  
Data meeting the setup time is clocked to the outputs with the rising  
edge of the Clock. The Output Enable input does not affect the states of  
the flip–flops, but when Output Enable is high, all device outputs are  
forced to the high–impedance state. Thus, data may be stored even when  
the outputs are not enabled.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 738–03  
1
DW SUFFIX  
SOIC PACKAGE  
CASE 751D–04  
20  
The HCT574A is identical in function to the HCT374A but has the  
flip–flop inputs on the opposite side of the package from the outputs to  
facilitate PC board layout.  
1
ORDERING INFORMATION  
Output Drive Capability: 15 LSTTL Loads  
TTL NMOS Compatible Input Levels  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 4.5 to 5.5 V  
Low Input Current: 1.0 µA  
MC54HCTXXXAJ  
MC74HCTXXXAN  
Ceramic  
Plastic  
MC74HCTXXXADW SOIC  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
PIN ASSIGNMENT  
Chip Complexity: 286 FETs or 71.5 Equivalent Gates  
OUTPUT  
ENABLE  
1
20  
V
CC  
D0  
D1  
D2  
2
3
4
19  
18  
17  
Q0  
Q1  
Q2  
LOGIC DIAGRAM  
2
3
4
5
19  
18  
17  
16  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
Q0  
D3  
D4  
5
16  
15  
14  
13  
12  
11  
Q3  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
6
Q4  
D5  
7
Q5  
NON–  
INVERTING  
OUTPUTS  
DATA  
INPUTS  
6
7
8
15  
14  
13  
D6  
8
Q6  
D7  
9
Q7  
GND  
10  
CLOCK  
9
11  
1
12  
D7  
Q7  
CLOCK  
PIN 20 = V  
CC  
PIN 10 = GND  
FUNCTION TABLE  
OUTPUT ENABLE  
Inputs  
Clock  
Output  
OE  
D
Q
Design Criteria  
Internal Gate Count*  
Value  
71.5  
1.5  
Units  
L
L
L
H
L
X
X
H
L
No Change  
Z
ea  
ns  
L,H,  
X
H
Internal Gate Propagation Delay  
Internal Gate Power Dissipation  
Speed Power Product  
X = don’t care  
Z = high impedance  
5.0  
µW  
pJ  
0.0075  
* Equivalent to a two–input NAND gate.  
3/97  
REV 7  
Motorola, Inc. 1997  

MC54HCT574AJ 替代型号

型号 品牌 替代类型 描述 数据表
MC74HCT574ANG ONSEMI

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