Datasheet > MC54HC589

MC54HC589

更新时间： 2024-10-15 11:08:55

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		移位寄存器栅
页数	文件大小	规格书
10页	262K
描述
8-Bit Serial or Parallel-Input/Serial-Output Shift Register with 3-State Output High-Performance Silicon-Gate CMOS

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MC54HC589 数据手册

SEMICONDUCTOR TECHNICAL DATA

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

High–Performance Silicon–Gate CMOS

The MC54/74HC589 is similar in function to the HC597, which is not a

3–state device. The device inputs are compatible with standard CMOS

outputs, with pullup resistors, they are compatible with LSTTL outputs.

This device consists of an 8–bit storage latch which feeds parallel data to

an 8–bit shift register. Data can also be loaded serially (see Function Table).

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

The shift register output, Q , is a three–state output, allowing this device to

be used in bus–oriented systems.

The HC589 directly interfaces with the Motorola SPI serial data port on

CMOS MPUs and MCUs.

D SUFFIX

SOIC PACKAGE

CASE 751B–05

•

Output Drive Capability: 15 LSTTL Loads

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 2 to 6 V

Low Input Current: 1 µA

ORDERING INFORMATION

High Noise Immunity Characteristic of CMOS Devices

In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

MC54HCXXXJ

MC74HCXXXN

MC74HCXXXD

Ceramic

Plastic

SOIC

•

Chip Complexity: 526 FETs or 131.5 Equivalent Gates

PIN ASSIGNMENT

LOGIC DIAGRAM

SERIAL

DATA

INPUT

SERIAL SHIFT/

PARALLEL LOAD

LATCH CLOCK

SHIFT CLOCK

= PIN 16

OUTPUT ENABLE

GND = PIN 8

PARALLEL

DATA

INPUTS

GND

DATA

LATCH

SHIFT

SERIAL

DATA

OUTPUT

LATCH CLOCK

SHIFT CLOCK

SERIAL SHIFT/

PARALLEL LOAD

OUTPUT ENABLE

10/95

Motorola, Inc. 1995

REV 6

3–1

12 3 4 5 6 7...10

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MC54HC589J	MOTOROLA	获取价格	8-Bit Serial or Parallel-Input/Serial-Output Shift Register with 3-State Output
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