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MC54HC589J PDF预览

MC54HC589J

更新时间: 2024-11-15 00:01:07
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 移位寄存器触发器逻辑集成电路
页数 文件大小 规格书
11页 129K
描述
8-Bit Serial or Parallel-Input/Serial-Output Shift Register with 3-State Output

MC54HC589J 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP,
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.62
Is Samacsys:N计数方向:RIGHT
系列:HC/UHJESD-30 代码:R-GDIP-T16
JESD-609代码:e0长度:19.495 mm
负载电容(CL):50 pF逻辑集成电路类型:PARALLEL IN SERIAL OUT
位数:8功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):53 ns认证状态:Not Qualified
座面最大高度:5.08 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:20 MHzBase Number Matches:1

MC54HC589J 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
J SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
High–Performance Silicon–Gate CMOS  
16  
1
The MC54/74HC589 is similar in function to the HC597, which is not a  
3–state device. The device inputs are compatible with standard CMOS  
outputs, with pullup resistors, they are compatible with LSTTL outputs.  
This device consists of an 8–bit storage latch which feeds parallel data to  
an 8–bit shift register. Data can also be loaded serially (see Function Table).  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
The shift register output, Q , is a three–state output, allowing this device to  
H
1
be used in bus–oriented systems.  
The HC589 directly interfaces with the Motorola SPI serial data port on  
CMOS MPUs and MCUs.  
D SUFFIX  
16  
SOIC PACKAGE  
CASE 751B–05  
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
1
Low Input Current: 1 µA  
ORDERING INFORMATION  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
MC54HCXXXJ  
MC74HCXXXN  
MC74HCXXXD  
Ceramic  
Plastic  
SOIC  
Chip Complexity: 526 FETs or 131.5 Equivalent Gates  
PIN ASSIGNMENT  
LOGIC DIAGRAM  
B
C
1
2
16  
15  
V
A
CC  
SERIAL  
14  
DATA  
S
A
D
E
F
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
S
A
INPUT  
SERIAL SHIFT/  
PARALLEL LOAD  
15  
LATCH CLOCK  
A
B
1
2
3
4
5
G
H
SHIFT CLOCK  
C
V
= PIN 16  
OUTPUT ENABLE  
CC  
GND = PIN 8  
PARALLEL  
DATA  
INPUTS  
D
E
F
GND  
Q
H
DATA  
LATCH  
SHIFT  
REGISTER  
6
7
G
SERIAL  
DATA  
OUTPUT  
9
H
Q
H
12  
LATCH CLOCK  
11  
13  
10  
SHIFT CLOCK  
SERIAL SHIFT/  
PARALLEL LOAD  
OUTPUT ENABLE  
10/95  
Motorola, Inc. 1995  
REV 6  

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