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MC54HC597AJ PDF预览

MC54HC597AJ

更新时间: 2024-11-15 00:01:07
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 移位寄存器触发器逻辑集成电路
页数 文件大小 规格书
12页 145K
描述
8-Bit Serial or Parallel-Input/Serial-Output Shift Register with Input Latch

MC54HC597AJ 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.82
Is Samacsys:N计数方向:RIGHT
系列:HC/UHJESD-30 代码:R-GDIP-T16
JESD-609代码:e0长度:19.495 mm
负载电容(CL):50 pF逻辑集成电路类型:PARALLEL IN SERIAL OUT
最大频率@ Nom-Sup:12000000 Hz位数:8
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
传播延迟(tpd):48 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Shift Registers
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:25 MHz
Base Number Matches:1

MC54HC597AJ 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
J SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
16  
1
High–Performance Silicon–Gate CMOS  
The MC54/74HC597A is identical in pinout to the LS597. The device  
inputs are compatible with standard CMOS outputs; with pullup resistors,  
they are compatible with LSTTL outputs.  
This device consists of an 8–bit input latch which feeds parallel data to an  
8–bit shift register. Data can also be loaded serially (see Function Table).  
The HC597A is similar in function to the HC589A, which is a 3–state  
device.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
1
D SUFFIX  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
16  
SOIC PACKAGE  
CASE 751B–05  
1
Low Input Current: 1 µA  
DT SUFFIX  
TSSOP PACKAGE  
CASE 948F–01  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
16  
1
Chip Complexity: 516 FETs or 129 Equivalent Gates  
ORDERING INFORMATION  
MC54HCXXXAJ  
Ceramic  
Plastic  
SOIC  
MC74HCXXXAN  
MC74HCXXXAD  
MC74HCXXXADT  
LOGIC DIAGRAM  
SERIAL  
14  
TSSOP  
DATA  
INPUT  
S
A
PIN ASSIGNMENT  
15  
1
A
B
B
C
1
2
16  
15  
V
A
S
CC  
2
3
4
5
C
PARALLEL  
DATA  
INPUTS  
D
E
F
D
E
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
A
INPUT  
LATCH  
SHIFT  
REGISTER  
SERIAL SHIFT/  
PARALLEL LOAD  
F
LATCH CLOCK  
SHIFT CLOCK  
RESET  
6
7
G
H
SERIAL  
DATA  
OUTPUT  
G
9
Q
H
H
12  
LATCH CLOCK  
GND  
Q
H
11  
SHIFT CLOCK  
PIN 16 = V  
PIN 8 = GND  
CC  
SERIAL SHIFT/ 13  
PARALLEL LOAD  
10  
RESET  
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.  
10/95  
REV 0  
Motorola, Inc. 1995  

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