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MC54HC259

更新时间： 2024-11-14 11:08:55
品牌 Logo 应用领域
飞思卡尔 - FREESCALE 解码器
页数 文件大小 规格书
7页 203K
描述
8-Bit Addressable Latch 1-of-8 Decoder

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MC54HC259 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
J SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
16  
16  
The MC54/74HC259 is identical in pinout to the LS259. The device inputs  
are compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
1
The HC259 has four modes of operation as shown in the mode selection  
table. In the addressable latch mode, the data on Data In is written into the  
addressed latch. The addressed latch follows the data input with all  
non–addressed latches remaining in their previous states. In the memory  
mode, all latches remain in their previous state and are unaffected by the  
Data or Address inputs. In the one–of–eight decoding or demultiplexing  
mode, the addressed output follows the state of Data In with all other outputs  
in the LOW state. In the Reset mode all outputs are LOW and unaffected by  
the address and data inputs. When operating the HC259 as an addressable  
latch, changing more than one bit of the address could impose a transient  
wrong address. Therefore, this should only be done while in the memory  
mode.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
1
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
16  
1
ORDERING INFORMATION  
MC54HCXXXJ  
MC74HCXXXN  
MC74HCXXXD  
Ceramic  
Plastic  
SOIC  
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
PIN ASSIGNMENT  
Low Input Current: 1 µA  
A0  
A1  
1
2
16  
15  
V
CC  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
RESET  
A2  
Q0  
Q1  
Q2  
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
ENABLE  
DATA IN  
Q7  
•
Chip Complexity: 202 FETs or 50.5 Equivalent Gates  
Q6  
LOGIC DIAGRAM  
Q5  
Q3  
GND  
Q4  
1
2
3
4
5
6
7
9
A0  
A1  
A2  
Q0  
Q1  
Q2  
Q3  
Q4  
ADDRESS  
INPUTS  
MODE SELECTION TABLE  
NONINVERTING  
OUTPUTS  
Enable Reset  
Mode  
L
H
L
H
H
L
Addressable Latch  
Memory  
8–Line Demultiplexer  
Reset  
13  
10  
11  
DATA IN  
Q5  
Q6  
12  
H
L
Q7  
15  
14  
LATCH SELECTION TABLE  
RESET  
ENABLE  
Address Inputs  
Latch  
C
B
A
Addressed  
PIN 16 = V  
CC  
PIN 8 = GND  
L
L
L
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
L
H
H
H
H
10/95  
REV 6  
Motorola, Inc. 1995  
1234567

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