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MC54HC273A PDF预览

MC54HC273A

更新时间: 2024-11-14 04:40:47
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器时钟
页数 文件大小 规格书
7页 111K
描述
OCTAL D FLIP-FLOP WITH COMMON CLOCK AND RESET

MC54HC273A 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
J SUFFIX  
CERAMIC PACKAGE  
CASE 732–03  
20  
20  
The MC54/74HC273A is identical in pinout to the LS273. The device  
inputs are compatible with standard CMOS outputs; with pullup resistors,  
they are compatible with LSTTL outputs.  
This device consists of eight D flip–flops with common Clock and Reset  
inputs. Each flip–flop is loaded with a low–to–high transition of the Clock  
input. Reset is asynchronous and active low.  
1
N SUFFIX  
PLASTIC PACKAGE  
CASE 738–03  
1
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
DW SUFFIX  
SOIC PACKAGE  
CASE 751D–04  
20  
1
1
Low Input Current: 1.0 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
DT SUFFIX  
TSSOP PACKAGE  
CASE 948E–02  
20  
Chip Complexity: 264 FETs or 66 Equivalent Gates  
ORDERING INFORMATION  
MC54HCXXXAJ  
MC74HCXXXAN  
MC74HCXXXADW  
MC74HCXXXADT  
Ceramic  
Plastic  
SOIC  
LOGIC DIAGRAM  
TSSOP  
2
3
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
5
6
4
7
PIN ASSIGNMENT  
8
9
DATA  
INPUTS  
RESET  
1
20  
V
CC  
NONINVERTING  
OUTPUTS  
13  
14  
17  
18  
12  
15  
16  
19  
Q0  
D0  
D1  
2
3
4
19  
18  
17  
Q7  
D7  
D6  
Q1  
Q2  
5
16  
15  
14  
13  
12  
11  
Q6  
11  
CLOCK  
6
Q5  
D2  
7
D5  
D3  
8
D4  
1
PIN 20 = V  
PIN 10 = GND  
CC  
RESET  
Q3  
9
Q4  
GND  
10  
CLOCK  
Design Criteria  
Value  
66  
Units  
ea  
Internal Gate Count*  
FUNCTION TABLE  
Inputs  
Reset Clock  
Output  
Internal Gate Propagation Delay  
Internal Gate Power Dissipation  
1.5  
ns  
D
Q
5.0  
µW  
pJ  
L
X
X
H
L
X
X
L
H
L
H
H
H
H
Speed Power Product  
.0075  
L
No Change  
No Change  
* Equivalent to a two–input NAND gate.  
2/97  
REV 7  
Motorola, Inc. 1997  

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