Datasheet > MC54HC259A

MC54HC259A

更新时间： 2024-11-14 00:01:07

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		解码器
页数	文件大小	规格书
9页	126K
描述
8-Bit Addressable Latch 1-of-8 Decoder

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MC54HC259A 数据手册

SEMICONDUCTOR TECHNICAL DATA

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

High–Performance Silicon–Gate CMOS

The MC54/74HC259A is identical in pinout to the LS259. The device

inputs are compatible with standard CMOS outputs; with pullup resistors,

they are compatible with LSTTL outputs.

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

The HC259A has four modes of operation as shown in the mode selection

table. In the addressable latch mode, the data on Data In is written into the

addressed latch. The addressed latch follows the data input with all

non–addressed latches remaining in their previous states. In the memory

mode, all latches remain in their previous state and are unaffected by the

Data or Address inputs. In the one–of–eight decoding or demultiplexing

mode, the addressed output follows the state of Data In with all other outputs

in the LOW state. In the Reset mode all outputs are LOW and unaffected by

the address and data inputs. When operating the HC259A as an

addressable latch, changing more than one bit of the address could impose

a transient wrong address. Therefore, this should only be done while in the

memory mode.

D SUFFIX

SOIC PACKAGE

CASE 751B–05

DT SUFFIX

TSSOP PACKAGE

CASE 948F–01

ORDERING INFORMATION

•

Output Drive Capability: 10 LSTTL Loads

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 2 to 6 V

MC54HCXXXAJ

Ceramic

Plastic

SOIC

MC74HCXXXAN

MC74HCXXXAD

MC74HCXXXADT

TSSOP

Low Input Current: 1 µA

High Noise Immunity Characteristic of CMOS Devices

In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

PIN ASSIGNMENT

•

Chip Complexity: 202 FETs or 50.5 Equivalent Gates

LOGIC DIAGRAM

RESET

ENABLE

DATA IN

ADDRESS

INPUTS

NONINVERTING

OUTPUTS

DATA IN

GND

RESET

PIN 16 = V

PIN 8 = GND

ENABLE

MODE SELECTION TABLE

LATCH SELECTION TABLE

Address Inputs

Enable Reset

Mode

Latch

Addressed

Addressable Latch

Memory

8–Line Demultiplexer

Reset

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

10/95

REV 0

Motorola, Inc. 1995

12 3 4 5 6 7...9

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与MC54HC259A相关器件

型号	品牌	获取价格	描述	数据表
MC54HC259AJ	MOTOROLA	获取价格	8-Bit Addressable Latch 1-of-8 Decoder
MC54HC259J	MOTOROLA	获取价格	8-Bit Addressable Latch 1-of-8 Decoder
MC54HC259JD	MOTOROLA	获取价格	D Latch, 1-Func, 8-Bit, CMOS, CDIP16
MC54HC259JDS	MOTOROLA	获取价格	IC,LATCH,SINGLE,8-BIT,HC-CMOS,DIP,16PIN,CERAMIC
MC54HC259JS	MOTOROLA	获取价格	D Latch, 1-Func, 8-Bit, CMOS, CDIP16
MC54HC259JS	ROCHESTER	获取价格	Jbar-Kbar Flip-Flop
MC54HC27	MOTOROLA	获取价格	Triple 3-Input NOR Gate
MC54HC273A	MOTOROLA	获取价格	OCTAL D FLIP-FLOP WITH COMMON CLOCK AND RESET
MC54HC273AJ	MOTOROLA	获取价格	Octal D Flip-Flop with Common Clock and Reset
MC54HC273DW	MOTOROLA	获取价格	HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, SOIC-20

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