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MC54HC259AJ PDF预览

MC54HC259AJ

更新时间: 2024-11-14 00:01:07
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 解码器
页数 文件大小 规格书
9页 126K
描述
8-Bit Addressable Latch 1-of-8 Decoder

MC54HC259AJ 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.7
其他特性:1:8 DMUX FOLLOWED BY LATCH; RESET ACTIVE ONLY WHEN LATCH ENABLE IS HIGH系列:HC/UH
JESD-30 代码:R-GDIP-T16JESD-609代码:e0
长度:19.495 mm负载电容(CL):50 pF
逻辑集成电路类型:D LATCH最大I(ol):0.0024 A
位数:1功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 VProp。Delay @ Nom-Sup:70 ns
传播延迟(tpd):45 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:LOW LEVEL
宽度:7.62 mmBase Number Matches:1

MC54HC259AJ 数据手册

 浏览型号MC54HC259AJ的Datasheet PDF文件第2页浏览型号MC54HC259AJ的Datasheet PDF文件第3页浏览型号MC54HC259AJ的Datasheet PDF文件第4页浏览型号MC54HC259AJ的Datasheet PDF文件第5页浏览型号MC54HC259AJ的Datasheet PDF文件第6页浏览型号MC54HC259AJ的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
J SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
High–Performance Silicon–Gate CMOS  
16  
16  
The MC54/74HC259A is identical in pinout to the LS259. The device  
inputs are compatible with standard CMOS outputs; with pullup resistors,  
they are compatible with LSTTL outputs.  
1
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
The HC259A has four modes of operation as shown in the mode selection  
table. In the addressable latch mode, the data on Data In is written into the  
addressed latch. The addressed latch follows the data input with all  
non–addressed latches remaining in their previous states. In the memory  
mode, all latches remain in their previous state and are unaffected by the  
Data or Address inputs. In the one–of–eight decoding or demultiplexing  
mode, the addressed output follows the state of Data In with all other outputs  
in the LOW state. In the Reset mode all outputs are LOW and unaffected by  
the address and data inputs. When operating the HC259A as an  
addressable latch, changing more than one bit of the address could impose  
a transient wrong address. Therefore, this should only be done while in the  
memory mode.  
1
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
16  
1
DT SUFFIX  
TSSOP PACKAGE  
CASE 948F–01  
16  
1
ORDERING INFORMATION  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
MC54HCXXXAJ  
Ceramic  
Plastic  
SOIC  
MC74HCXXXAN  
MC74HCXXXAD  
MC74HCXXXADT  
TSSOP  
Low Input Current: 1 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
PIN ASSIGNMENT  
Chip Complexity: 202 FETs or 50.5 Equivalent Gates  
A0  
A1  
1
2
16  
15  
V
CC  
LOGIC DIAGRAM  
RESET  
A2  
Q0  
Q1  
Q2  
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
ENABLE  
DATA IN  
Q7  
1
2
3
4
5
6
7
9
A0  
A1  
A2  
Q0  
Q1  
Q2  
Q3  
Q4  
ADDRESS  
INPUTS  
NONINVERTING  
OUTPUTS  
Q6  
Q5  
13  
10  
11  
Q3  
DATA IN  
Q5  
Q6  
GND  
Q4  
12  
Q7  
15  
14  
RESET  
PIN 16 = V  
CC  
PIN 8 = GND  
ENABLE  
MODE SELECTION TABLE  
LATCH SELECTION TABLE  
Address Inputs  
Enable Reset  
Mode  
Latch  
C
B
A
Addressed  
L
H
L
H
H
L
Addressable Latch  
Memory  
8–Line Demultiplexer  
Reset  
L
L
L
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
H
L
L
H
H
H
H
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.  
10/95  
REV 0  
Motorola, Inc. 1995  

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